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ADS7608A4A-5 参数 Datasheet PDF下载

ADS7608A4A-5图片预览
型号: ADS7608A4A-5
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM ( 4M ×8位×4银行) [Synchronous DRAM(4M X 8 Bit X 4 Banks)]
分类和应用: 动态存储器
文件页数/大小: 8 页 / 635 K
品牌: A-DATA [ A-DATA TECHNOLOGY ]
 浏览型号ADS7608A4A-5的Datasheet PDF文件第1页浏览型号ADS7608A4A-5的Datasheet PDF文件第2页浏览型号ADS7608A4A-5的Datasheet PDF文件第3页浏览型号ADS7608A4A-5的Datasheet PDF文件第4页浏览型号ADS7608A4A-5的Datasheet PDF文件第5页浏览型号ADS7608A4A-5的Datasheet PDF文件第7页浏览型号ADS7608A4A-5的Datasheet PDF文件第8页  
A-Data
AC Characteristics
-5
Parameter
System clock /CAS Latency = 3
Cycle time
/CAS Latency = 2
Symbol
Min
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tRC
tRRC
tRCD
tRAS
tRP
tRRD
tCCD
5
1000
10
2
2
-
-
55
55
15
40
15
10
1
0
1
5
2
0
1.5
1.5
1
1.5
1
1.5
1
1.5
1
1
2
1
1
64
-
-
4.5
6
-
-
-
10
2.25
2.25
-
-
55
55
16.5
-
-
5
6
-
-
-
Clock high pulse width
Clock low pulse width
Access time
form clock
/RAS cycle
time
/CAS Latency = 3
/CAS Latency = 2
Operation
Auto Refresh
Max
Min
5.5
1000
10
2.5
2.5
-
-
60
60
18
42
18
12
1
0
1
5
2
0
2.7
1.5
1
1.5
1
1.5
1
1.5
1
1
2
1
1
64
-
-
5.4
6
-
-
-
100K
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
Min
6
1000
10
2.5
2.5
-
-
62
62
20
42
20
14
1
0
1
4
2
0
2.7
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
1
1
64
-
-
5.4
6
-
-
-
120K
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
Min
7
1000
Max
-5.5
-6
-7
ADS7608A4A
-7.5
Unit Note
Min
7.5
1000
7.5
2.5
2.5
-
-
65
65
15
45
15
15
1
0
1
4
2
0
2.7
1.5
1
1.5
1
1.5
1
1.5
1
1.5
1
1
1
64
-
-
5.4
ns
5.4
-
ns
-
-
120K
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
CLK
CLK
CLK
CLK
CLK
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
ms
3
1
1
1
1
1
1
1
1
2
ns
ns
1
1
ns
Max
/RAS to /CAS delay
/RAS active time
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
100K 38.5 100K
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16.5
11
1
0
1
5
2
0
2
1.5
1
1.5
1
1.5
1
1.5
1
1
2
1
1
64
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write command to data – in delay tWTL
Data – in to precharge command
Data – in active command
DQM to data – out Hi-Z
DQM to data – in mask
Data – out hold time
Data – input setup time
Data – input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
MRS to new command
Power down exit time
Self refresh exit time
Refresh time
tDPL
tDAL
tDQZ
tDQM
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tMRD
tPDE
tSRE
tREF
Note :
1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1 April, 2001
6