V-Data
Synchronous DRAM
General Description
The VDS4616A4A are two-bank Synchronous
DRAMs organized as 524,288 words x 16 bits x 2
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
VDS4616A4A
512K x 16 Bit x 2 Banks
Features
•Single
3.3V +/- 0.3V power supply
•MRS
Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8, & full page)
-Burst Type (sequential & Interleave)
•2
banks operation
•All
inputs are sampled at the positive edge of
the system clock
•Burst
Read single write operation
•Auto
& Self refresh
•4096
refresh cycle
•DQM
for masking
•Package:50-pins
400 mil TSOP-Type II
Ordering Information.
Part No.
VDS4616A4A-5
VDS4616A4A -6
VDS4616A4A -7
Frequency
200Mhz
166Mhz
143Mhz
Interface
LVTTL
LVTTL
LVTTL
Package
400mil 50pin TSOPII
400mil 50pin TSOPII
400mil 50pin TSOPII
Pin Assignment
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
/WE
/CAS
/RAS
/CS
(BS)A11
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
Vss
Q
DQ13
DQ12
V
DD Q
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
50-pin plastic TSOP II 400 mil
Rev 1 December, 2001
1
A-DATA [ A-DATA TECHNOLOGY ]
