Ai9943
Serial Interface
Serial Write Operation
NOTE: 1. SDATA bits are internally latched on the rising edges of SCK.
2. System update of loaded registers occurs on SL rising edge.
3. All 12 data bits D0-D11 must be written. If the register contains fewer than 12 bits, zeros
should be used for undefined bits.
4. Test bit is for internal use only and must be set low.
Continuous Serial Write Operation to All Registers
NOTE: 1. Multiple sequential registers may be loaded continuously.
2. The first (LOWEST address) register address is written, followed by multiple 12-bit data-words.
3. The address automatically increments with each 12-bit data-word. (All 12 bits must be written.)
4. SL is held LOW until the last desired register has been loaded.
5. New data is updated at the next SL rising edge.
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