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EI16C550 参数 Datasheet PDF下载

EI16C550图片预览
型号: EI16C550
PDF下载: 下载PDF文件 查看货源
内容描述: FIFO UART [FIFO UART]
分类和应用: 先进先出芯片
文件页数/大小: 2 页 / 47 K
品牌: A1PROS [ A1 PROS CO., LTD. ]
 浏览型号EI16C550的Datasheet PDF文件第2页  
Ei16C550
FIFO UART
Semiconductor, Inc.
FEATURES
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5V Operation
Full duplex asynchronous receiver and transmitter
Easily interfaces to most popular micro-
processors
Adds or deletes standard asynchronous
communication bits (start, stop, and parity) to or
from a serial data stream
Independently controlled transmitter, receiver,
line status, and data set interrupts
Programmable baud rate generator allows
division of any input clock by 1 to (2
16
-1) and
generates the internal 16 x clock
Independent receiver clock input
MODEM control functions (CTS, RTS, DSR,
DTR, RI,and DCD)
Fully programmable serial interface
characteristics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
False start bit detection
Complete status reporting capabilities
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Tri-StateÆTTL drive capabilities for bi-
directional data bus and control bus
Line break generation and detection
Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity overrun, and framing error simulation
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Fully prioritized interrupt systems controls
16 byte FIFO for reduced CPU overhead
DESCRIPTION
The Epic Ei16C550 Universal Asynchronous Receiver
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
The UART performs serial to parallel conversion on
data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversions on data charac-
ters received from the CPU. The CPU can read the complete
status of the UART at any time during the functional operation.
Status information reported includes the type and condition of
the transfer operation being performed by the UART, as well
as any error conditions (party, overrun, framing, or break
detect).
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Part Numbers May Be Marked With "IMP" or "Ei."
PIN CONFIGURATION
DSR
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CTS
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38
VCC
CD
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N.C.
D4
D3
D2
D1
D0
NC
VCC
RIï
DCDï
DSRï
CTSï
XTAL1
XTAL2
DOSTRï
DOSTR
VSS
NC
DISTRï
DISTR
DDIS
TXRDYï
ADSï
XTAL1
XTAL2
-IOW
GND
N.C.
IOW
IOR
IOR
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N.C.
DDIS
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40-PIN DIP
44-PIN PLCC
48-PIN TQFP
7
TXRDY
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AS
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2ï
BAUDOUTï
XTAL1
XTAL2
DOSTRï
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
E
i
1
6
C
5
5
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
RIï
DCDï
DSRï
CTSï
MR
OUT1ï
DTRï
RTSï
OUT2ï
INTRPT
RXRDYï
A0
A1
A2
ADSï
TXRDYï
DDIS
DISTR
DISTRï
48
47
46
45
44
43
42
41
40
39
6
5
4
3
2
1
44
43
42
41
40
37
36
35
34
33
32
N.C.
RI
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D4
D3
D2
D1
D0
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
17
18
19
20
21
22
23
24
N.C.
RESET
OP1
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DTR
ï
RTS
ï
OP2
ï
INT
RXRDY
ï
A0
A1
A2
N.C.
18
19
20
21
22
23
24
25
26
27
28
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2ï
BAUD-
OUTï
7
8
9
10
11
12
13
14
15
16
17
Ei16C550
39
38
37
36
35
34
33
32
31
30
29
MR
OUT1ï
DTRï
RTSï
OUT2ï
NC
INTRPT
RXRDYï
A0
A1
A2
D5
D6
D7
RCLK
N.C.
RX
TX
CS0
CS1
CS2
ï
BAUDOUT
ï
Ei16C550
31
30
29
28
27
26
25