AC Electrical Characteristics † - Clock Timing (Figures 12 and 13)
Characteristics
Sym
Min Typ ‡ Max
Units
Test Conditions
1 Clock Period*
t
CLK
220
244
300
ns
2 Clock Width High
t
CH
95
122
150
ns
3 Clock Width Low
t
CL
110
122
150
ns
4 Clock Transition Time
t
CTT
20
ns
5 Frame Pulse Setup TIme
t
CCT
20
ns
6 Frame Pulse Hold Time
t
FPH
0.020
670
µs
7 Frame Pulse Width
t
FPW
244
ns
†† Timing is over recommended temperature & power supply voltages.
‡
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*
Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high
impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i
.
Figure 12 Frame Allignment
C4i
FOi
Bit
Cells
Channel 31
Bit 0
Channel 0
Bit 7
Figure 13 Clock Timing
t
CLK
t
CL
C4i
2.0V
0.8V
t
CHL
t
FPH
F0i
2.0V
0.8V
t
FPW
t
FPS
t
CTT
t
FPH
t
FPS
t
CTT
t
CH
9
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