AAT3242
300mA/150mA Dual CMOS LDO Linear Regulator
Pin Descriptions
Pin #
Symbol
Function
1
ENA
Enable Regulator A pin; this pin should not be left floating. When pulled
low, the PMOS pass transistor turns off and the device enters shutdown
mode, consuming less than 1µA.
2, 3, 8, 9
4
GND
Ground connection pins.
POKA
Power OK pin with open drain output. It is pulled low when the OUTA pin is
below the 10% regulation window.
5
6
7
OUTB
INB
Low current (150mA) regulator output pin; should be decoupled with a
2.2µF or greater output low-ESR ceramic capacitor.
Input voltage pin for Regulator B; should be decoupled with 1µF or greater
capacitor.
ENB
Enable Regulator B; this pin should not be left floating. When pulled low, the
PMOS pass transistor turns off and the device enters shutdown mode, con-
suming less than 1µA.
10
11
12
POKB
OUTA
INA
Power OK pin with open drain output. It is pulled low when the OUTB pin is
below the 10% regulation window.
High-current (300mA) regulator output pin; should be decoupled with a
2.2µF or greater output low-ESR ceramic capacitor.
Input voltage pin for Regulator A; should be decoupled with 1µF or greater
capacitor.
Pin Configuration
TSOPJW-12
(Top View)
1
2
3
4
5
6
12
11
10
9
ENA
GND
GND
POKA
OUTB
INB
INA
OUTA
POKB
GND
GND
ENB
8
7
2
3242.2006.04.1.10
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
