AAT3236
300mA CMOS High Performance LDO
tion to ground and the LDO regulator ground con-
nection. When the high load current returns through
this path, a small ripple voltage is created, feeding
into the CBYP loop.
any load noise or ripple current feedback through
the LDO regulator.
Evaluation Board Layout
Figure 2 shows the preferred method for the
bypass and output capacitor connections. For low
output noise and highest possible power supply
ripple rejection performance, it is critical to connect
the bypass and output capacitor directly to the LDO
regulator ground pin. This method will eliminate
The AAT3236 evaluation layout (Figures 3, 4, and
5) follows the recommend printed circuit board lay-
out procedures and can be used as an example for
good application layouts.
Note: Board layout shown is not to scale.
ILOAD
IIN
VIN
VOUT
VIN
LDO
Regulator
EN
BYP
GND
IGND
DC INPUT
CBYP
COUT
RLOAD
CIN
CBYP
IRIPPLE
IBYP + noise
GND
LOOP
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 1: Common LDO Regulator Layout with CBYP Ripple Feedback Loop.
ILOAD
IIN
VIN
EN
VOUT
BYP
VIN
LDO
Regulator
GND
IGND
CBYP
COUT
RLOAD
DC INPUT
GND
CIN
IBYP only
IRIPPLE
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 2: Recommended LDO Regulator Layout.
14
3236.2007.03.1.4
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
