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AK681024G-70LL 参数 Datasheet PDF下载

AK681024G-70LL图片预览
型号: AK681024G-70LL
PDF下载: 下载PDF文件 查看货源
内容描述: 1048579 ×8位CMOS静态随机存取存储器 [1,048,579 x 8 Bit CMOS Static Random Access Memory]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 2 页 / 164 K
品牌: ACCUTEK [ ACCUTEK MICROCIRCUIT CORPORATION ]
 浏览型号AK681024G-70LL的Datasheet PDF文件第2页  
DESCRIPTION
Accutek
Microcircuit
Corporation
AK681024G
1,048,579 x 8 Bit CMOS
Static Random Access Memory
The Accutek AK681024G is a high density SRAM memory module
organized in 1 Meg X 8 bit words. The assembly consists of four me-
dium speed 128K X 8 SRAMs in thin TSOP packages, plus a CMOS
decoder logic IC and four decoupling capacitor chips, mounted on
the front side and four medium speed 128K x 8 SRAMS in thin
TSOP packages and four decoupling capacitor chips mounted on
the back side of a low-profile printed circuit board. The module con-
figuration is a 36 pin leaded SIP.
The memory operates as a single asynchronous 1 Meg X 8 SRAM
from a 5V supply, and has common I/O, chip enable, output enable
and write enable functions. With the proper choice of SRAMs, it is
available in three separate low-standby-power configurations, with
access times of 55, 70, 85 or 100 nSEC.
The combination of low power, low profile and high density packag-
ing offered by the AK681024G makes it ideal for use in applications
where board space and available power are limited and extremely
low access times are not required. It is especially useful in VMEbus
designs and in places where very close module-to-module spacing
is dictated.
1
36
·
Range of access times from 55 to 100 nSEC
·
Low, low-low and ultra-low standby power level versions avail-
able
·
Single 5 volt power supply - AK681024G
·
Single 3.3 volt power supply - AK681024G/3.3
·
Operating free air temerature 0
0
C to 70
0
C (Industrial range
version of -10
0
C to 85
0
C also available)
·
Completely static and asynchronous, no clock or timing strobe
required
·
Low
9.0 Watt Max Active
120 µ Watt Max Standby
Low Low
9.0 Watt Max Active
80 µ Watt Standby
FEATURES
·
1,048,576 x 8 bit organization
·
JEDEC Standard 36 pin SIP format
·
Common I/O, single OE, CE and WE functions
·
Low 0.550 inch maximum seated height and thin profile allow
maximum board density
PIN NOMENCLATURE
DQ
0
- DQ
7
A
0
- A
19
CE
WE
OE
Vcc
Vss
NC
Data In/Data Out
Address Inputs
Chip Enable
Write Enable
Output Enable
5v Supply
Ground
No Connection
PIN ASSIGNMENT
PIN #
SYMBOL
PIN #
SYMBOL
PIN #
SYMBOL
PIN #
SYMBOL
FUNCTIONAL DIAGRAM
CE
A
15
A
16
A
12
A
18
A
6
DQ
1
Vss
A
0
28
29
30
31
32
33
34
35
36
A
7
A
8
A
9
DQ
7
DQ
4
DQ
6
A
17
Vcc
OE
1
2
3
4
5
6
7
8
9
NC
Vcc
WE
DQ
2
DQ
3
DQ
0
A
1
A
2
A
3
10
11
12
13
14
15
16
17
18
A
4
Vss
DQ
5
A
10
A
11
A
5
A
13
A
14
A
19
19
20
21
22
23
24
25
26
27
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
128K x 8 SRAM
Leaded SIP: AK681024G
DECODER
A19
A18
A17
CE
OE
WE
A
0
- A
16
DQ
0
- DQ
7
MODULE OPTIONS