ACE24C04/08A
Two-wire Serial EEPROM
Figure 6．Output Acknowledge
Device Addressing
The 4/8K EEPROM devices all require an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 7).
The device address word consists of a mandatory one, zero sequence for the first four most
significant bits as shown. This is common to all the EEPROM devices.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory
page address bit. The two device address bits must compare to their corresponding hard -wired input
pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page
addressing. The A2 must compare to its corresponding hard-wired input pin. The A1 and A0 pins are
no connect.
The module package device address word also consist of a mandatory one, zero sequence for the
first four most significant bits. The next 3 bits are all zero.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the
chip will return to a standby state.
Write Operations
Byte Write
A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a
zero and the addressing device, such as a microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an internally timed write cycle, t
WR,
to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (refer to Figure 8).
VER 1.5
8
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