ACE93C46.56.66
Three-wire Serial EEPROM
Instruction Set for the ACE93C56/66
Instruction SB
READ
EWEN
REASE
WRITE
1
1
1
1
OP
Code
10
00
11
01
Address
*8
A
8
-A
0
11XXXXXX
A
8
-A
0
A
8
-A
0
*16
A
7
-A
0
11XXXXXX
A
7
-A
0
A
7
-A
0
D
7
-D
0
D
15
-D
0
*8
Data
*16
Comments
Read data stored in memory,
at specified address
Write enable must precede all
programming modes
Erase memory location
An-A0
Writes memory location
An-A0
Erases all memory locations.
Valid only at VCC=4.5V to
5.5V
Writes all memory locations.
Valid only at VCC=4.5V to
5.5V
Disables all programming
instructions
ERAL
1
00
10XXXXXXX 10XXXXXX
WRAL
1
00
01XXXXXXX 01XXXXXX D
7
-D
0
D
15
-D
0
00XXXXXXX 00XXXXXX
EWDS
1
00
Notes: The X’s in the address field represent don’t care values and must be clocked.
READ (READ):
The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and
address are decoded, data from the selected memory location is available at the serial output pin DO. Output data
changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”)
precedes the 8- or 16-bit data output string. The ACE93C56/66 supports sequential read operations. The device will
automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high .In this case ,the dummy bit (logic “0”)will not be clocked out between memory locations, thus allowing for a
continuous steam of data to be read.
ERASE/WRITE (EWEN):
To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first
applied. An Erase/Write Enable(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is
executed or VCC power is removed from the part.
ERASE (ERASE):
The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The
self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A logic “1” at pin
DO indicates that the selected memory location has been erased, and the part is ready for another instruction.
VER 1.5
7
ACE [ ACE TECHNOLOGY CO., LTD. ]
