Equivalent Capacitance
C
EQM
C
EQI
C
EQO
C
EQCR
C
L
f
m
f
n
f
p
f
q1
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in pF
= Equivalent capacitance of routed array clock in
pF
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz (All
families)
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Power (uW) = C
EQ
* V
CC2
* F
Where:
C
EQ
is the equivalent capacitance expressed in pF.
V
CC
is the power supply in volts.
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring I
CC
active
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of V
CC
. Equivalent
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
C
EQ
Values for Actel FPGAs
(1)
Fixed Capacitance Values for Actel FPGAs
(pF)
Device Type
A1010B
A1020B
3.7
22.1
31.2
4.6
A1010B
A1020B
A10V10B
A10V20B
r
1
routed_Clk1
41.4
68.6
40
65
A10V10B
A10V20B
Modules (C
EQM
)
Input Buffers (
CEQI
)
Output Buffers (C
EQO
)
Routed Array Clock Buffer
Loads (C
EQCR
)
3.2
10.9
11.6
4.1
Determining Average Switching Frequency
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Power = V
CC2
* [(m * C
EQM
* f
m
)
modules
+
(n * C
EQI
* f
n
)
inputs
+ (p * (C
EQO
+ C
L
) * f
p
)
outputs
+
0.5 * (q
1
* C
EQCR
* f
q1
)
routed_Clk1
+
(r
1
* f
q1
)
routed_Clk1
]
Where:
m
n
p
q
1
r
1
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
= Number of clock loads on the first routed array
clock (All families)
= Fixed capacitance due to first routed array
clock (All families)
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Logic Modules (m)
Inputs switching (n)
Outputs switching (p)
First routed array clock loads (q
1
)
Load capacitance (C
L
)
Average input switching rate (f
n
)
Average output switching rate (f
p
)
90% of modules
#inputs/4
#outputs/4
40% of modules
35 pF
F/5
F/10
(2)
Average logic module switching rate (f
m
) F/10
Average first routed array clock rate F
(f
q1
)
1-290
ACTEL [ Actel Corporation ]
