A C T
™
1 Seri es FP GA s
Pa ckag e Therm al C haract er is tic s
The device junction to case thermal characteristics is
θ
jc, and the junction to ambient air characteristics is
θ
ja. The
thermal characteristics for
θ
ja are shown with two different
air flow rates. Maximum junction temperature is 150°C.
A sample calculation of the maximum power dissipation for
an 84-pin plastic leaded chip carrier at commercial
temperature is as follows:
Max junction temp.
( °
C
)
– Max commercial temp.
( °
C
)
150
°
C – 70
°
C
------------------------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.2 W
-
-
θ
ja
( °
C
⁄
W
)
37
°
C
⁄
W
Package Type
Plastic J-Leaded Chip Carrier
Plastic Quad Flatpack
Very Thin (1.0 mm) Quad Flatpack
Ceramic Pin Grid Array
Ceramic Quad Flatpack
Pin Count
44
68
84
100
80
84
84
θjc
15
13
12
13
12
8
5
θja
Still Air
45
38
37
48
43
33
40
θja
300 ft/min
35
29
28
40
35
20
30
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Gener al Power Equati on
P = [I
CC
standby + I
CC
active] * V
CC
+ I
OL
* V
OL
* N + I
OH
*
(V
CC
– V
OH
) * M
Where:
I
CC
standby is the current flowing when no inputs or
outputs are changing.
I
CC
active is the current flowing due to CMOS switching.
I
OL
, I
OH
are TTL sink/source currents.
V
OL
, V
OH
are TTL level output voltages.
N equals the number of outputs driving TTL loads to
V
OL
.
M equals the number of outputs driving TTL loads to
V
OH
.
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided into
two components: static and active.
Static Power Component
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst case conditions.
I
CC
3 mA
1 mA
0.75 mA
0.30 mA
V
CC
5.25 V
5.25 V
3.60 V
3.30 V
Power
15.75 mW (max)
5.25 mW (typ)
2.70 mW (max)
0.99 mW (typ)
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the active
power dissipation is the totem-pole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with frequency
and voltage to represent active power dissipation.
Actel FPGAs have small static power components that result
in lower power dissipation than PALs or PLDs. By integrating
multiple PALs/PLDs into one FPGA, an even greater
reduction in board-level power dissipation can be achieved.
1-289
ACTEL [ Actel Corporation ]
