A C T
™
1 Seri es FP GA s
Fu nctio nal Ti mi ng T ests
AC timing for logic module internal delays is determined
after place and route. The DirectTime Analyzer utility
displays actual timing parameters for circuit delays. ACT 1
devices are AC tested to a “binning” circuit specification.
The circuit consists of one input buffer + n logic modules +
one output buffer (n = 16 for A1010B; n = 28 for A1020B). The
logic modules are distributed along two sides of the device, as
inverting or non-inverting buffers. The modules are
connected through programmed antifuses with typical
capacitive loading.
Propagation delay [t
PD
= (t
PLH
+ t
PHL
)/2] is tested to the
following AC test specifications.
Outpu t Buffer P er formance D e rati ng (5V )
Sink
12
–4
Source
10
I
OH
(mA)
0.3
0.4
V
OL
(Volts)
0.5
0.6
I
OL
(mA)
–6
8
–8
6
–10
4
0.2
–12
4.0
3.6
3.2
2.8
2.4
2.0
V
OH
(Volts)
Military, worst-case values at 125°C, 4.5 V.
Commercial, worst-case values at 70°C, 4.75 V.
Note:
The above curves are based on characterizations of sample devices and are not completely tested on all devices.
Outpu t Buffer P er formance D e rati ng (3. 3V)
Sink
12
–4
Source
10
I
OH
(mA)
0.1
0.2
V
OL
(Volts)
0.3
0.4
I
OL
(mA)
–6
8
–8
6
–10
4
0.0
–12
0
0.5
1.0
1.5
2.0
2.5
V
OH
(Volts)
Commercial, worst-case values at 70°C, 4.75 V.
Note:
The above curves are based on characterizations of sample devices and are not completely tested on all devices.
1-291
ACTEL [ Actel Corporation ]
