v4.0.1
ACT
™
2 Family FPGAs
Fe a t ur es
• Up to 8000 Gate Array Gates
(20,000 PLD equivalent gates)
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL
®
Packages
• Datapath Performance at 105 MHz
• 16-Bit Accumulator Performance to 39 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0-micron CMOS Technology
• Design Library with over 500 Macro Functions
• Single-Module Sequential Functions
• Wide-Input Combinatorial Functions
• Up to 1232 Programmable Logic Modules
• Up to 998 Flip-Flops
Pr od uc t F am i l y P r o f i l e
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Logic Modules
S-Modules
C-Modules
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
User I/Os (maximum)
Packages
1
A1225A
2,500
6,250
63
25
451
231
220
382
36
15
250,000
83
100 CPGA
100 PQFP
100 VQFP
84 PLCC
A1240A
4,000
10,000
100
40
684
348
336
568
36
15
400,000
104
132 CPGA
144 PQFP
176 TQFP
84 PLCC
A1280A
8,000
20,000
200
80
1,232
624
608
998
36
15
750,000
140
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
85 MHz
67 MHz
36 MHz
Performance
2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
105 MHz
70 MHz
39 MHz
100 MHz
69 MHz
38 MHz
Notes:
1. See the
for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
D e ce m b e r 2 0 0 0
1
© 2000 Actel Corporation
ACTEL [ Actel Corporation ]
