H iR e l F PG A s
Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
The device junction to case thermal characteristic is
θ
jc
, and
the junction to ambient air characteristic is
θ
ja
. The thermal
characteristics for
θ
ja
are shown with two different air flow
rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a CPGA 176-pin package at military
temperature is as follows:
Max. junction temp. (°C) – Max. military temp. = 150°C – 125°C = 1.1 W
-----------------------------------------------------------------------------------------------------------------
-
------------------------------------
23°C/W
θ
ja
(°C/W)
θ
ja
Still Air
33
25
25
23
21
15
40
35
25
23
20
θ
ja
300 ft/min
20
16
15
12
10
8
30
25
20
15
10
Package Type
Ceramic Pin Grid Array
Pin Count
84
132
133
176
207
257
84
132
172
196
256
θ
jc
6.0
4.8
4.8
4.6
3.5
2.8
7.8
7.2
6.8
6.4
6.2
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Ceramic Quad Flat Pack
Po w e r D i s s i pa t i o n
Gener al P ow er E quat i on
P = [I
CC
standby + I
CC
active] * V
CC
+ I
OL
* V
OL
* N +
I
OH
* (V
CC
– V
OH
) * M
where:
I
CC
standby is the current flowing when no inputs or outputs
are changing.
I
CC
active is the current flowing due to CMOS switching.
I
OL
, I
OH
are TTL sink/source currents.
V
OL
, V
OH
are TTL level output voltages.
N equals the number of outputs driving TTL loads to
V
OL
.
M equals the number of outputs driving TTL loads to
V
OH
.
Accurate values for N and M are difficult to determine
because they depend on the family type, on the design, and on
the system I/O. The power can be divided into two
components—static and active.
S tat i c P ow er Co m ponen t
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst-case conditions.
Family
ACT 3
1200XL/3200DX
ACT 2
ACT 1
I
CC
2 mA
2 mA
2 mA
3 mA
V
CC
5.25V
5.25V
5.25V
5.25V
Power
10.5 mW
10.5 mW
10.5 mW
15.8 mW
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all
outputs driving low, and 140 mW with all outputs driving high.
Ac ti ve P ower Com po nent
Actel FPGAs have small static power components that result
in power dissipation lower than that of PALs or PLDs. By
integrating multiple PALs or PLDs into one FPGA, an even
greater reduction in board-level power dissipation can be
achieved.
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totempole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
11
ACTEL [ Actel Corporation ]
