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A3P060-1FGG144 参数 Datasheet PDF下载

A3P060-1FGG144图片预览
型号: A3P060-1FGG144
PDF下载: 下载PDF文件 查看货源
内容描述: 闪光的ProASIC3系列FPGA [ProASIC3 Flash Family FPGAs]
分类和应用:
文件页数/大小: 206 页 / 5922 K
品牌: ACTEL [ Actel Corporation ]
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v1.0
ProASIC3 Flash Family FPGAs
with Optional Soft ARM
®
Support
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
®
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
Clock Conditioning Circuit (CCC) and PLL
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X
and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase-Shift,
Multiply/Divide,
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Delay
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC
®
3
devices) via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Embedded Memory
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
ProASIC3 Product Family
ProASIC3 Devices
ARM7 Devices
1
Cortex-M1 Devices
1
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
2
Integrated PLL in CCCs
VersaNet Globals
3
I/O Banks
Maximum User I/Os
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
A3P015
A3P030
A3P060
A3P125
A3P250
M1A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
QN132
5
VQ100
PQ208
FG144/256
5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
A3P400
M1A3P400
400 k
9,216
54
12
1k
Yes
1
18
4
194
A3P600
M1A3P600
600 k
13,824
108
24
1k
Yes
1
18
4
235
A3P1000
M7A3P1000
M1A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
300
15 k
128
384
1k
6
2
49
QN68
30 k
256
768
1k
6
2
81
QN132
VQ100
60 k
512
1,536
18
4
1k
Yes
1
18
2
96
QN132
VQ100
TQ144
FG144
125 k
1,024
3,072
36
8
1k
Yes
1
18
2
133
QN132
VQ100
TQ144
PQ208
FG144
Notes:
1. Refer to the
datasheet or
product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the
handbook.
5. The M1A3P250 device does not support this package.
† A3P015 and A3P030 devices do not support this feature.
February 2008
© 2008 Actel Corporation
‡ Supported only by A3P015 and A3P030 devices.
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