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A3P250-FG144T 参数 Datasheet PDF下载

A3P250-FG144T图片预览
型号: A3P250-FG144T
PDF下载: 下载PDF文件 查看货源
内容描述: 汽车的Flash的ProASIC3系列FPGA [Automotive ProASIC3 Flash Family FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 136 页 / 4329 K
品牌: ACTEL [ Actel Corporation ]
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v1.0
Automotive ProASIC3 Flash Family FPGAs
Features and Benefits
High-Temperature AEC-Q100–Qualified Devices
• Grade 2 105°C T
A
(115°C T
J
)
• Grade 1 125°C T
A
(135°C T
J
)
• PPAP Documentation
®
Low Power
• 1.5 V Core Voltage
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Firm-Error Immune
• Only Automotive FPGAs to Offer Firm-Error Immunity
• Can Be Used without Configuration Upset Risk
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and A3P1000)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the Automotive ProASIC
®
3
Family
High Capacity
• 60 k to 1 M System Gates
• Up to 144 kbits of SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interface
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 350 MHz)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents (anti-tampering)
SRAMs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
Automotive ProASIC3 Product Family
ProASIC3 Devices
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals*
I/O Banks
Maximum User I/Os
Package Pins
VQFP
FBGA
A3P060
60 k
1,536
18
4
1k
Yes
1
18
2
96
VQ100
FG144
A3P125
125 k
3,072
36
8
1k
Yes
1
18
2
133
VQ100
FG144
A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
VQ100
FG144, FG256
A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
300
FG144, FG256, FG484
Note:
*Six chip-wide (main) globals and three additional global networks in each quadrant are available.
January 2008
© 2008 Actel Corporation
I