v3.1
40MX and 42MX Automotive FPGA Families
Features
High Capacity
•
•
•
•
•
Single-Chip ASIC Alternative for Automotive
Applications
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
Ease of Integration
•
•
•
•
•
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
Maximum User I/Os
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
A40MX02
3,000
–
–
295
–
–
–
147
1
57
–
68
100
80
–
A40MX04
6,000
–
–
547
–
–
–
273
1
69
–
84
100
80
–
A42MX09
14,000
–
348
336
–
–
348
516
2
104
–
84
100, 160
100
176
A42MX16
24,000
–
624
608
–
–
624
928
2
140
–
–
208
100
176
A42MX24
36,000
–
954
912
24
–
954
1,410
2
176
Yes
–
160, 208
–
176
A42MX36
54,000
2,560
1,230
1,184
24
10
1,230
1,822
6
202
Yes
–
208, 240
–
–
Note:
While the automotive-grade MX devices are offered in standard speed grade only, the MX family is also offered in commercial,
industrial and military temperature grades with -F, Std, -1, -2 and -3 speed grades. Refer to the
datasheet for more details.
May 2006
© 2006 Actel Corporation
i
See the Actel website (www.actel.com) for the latest version of this datasheet.
ACTEL [ Actel Corporation ]
