SX Family FPGAs
PCI Compliance for the SX Family
The SX family supports 3.3 V and 5.0 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.
Table 1-6 •
Symbol
V
CCA
V
CCR
V
CCI
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
C
IN
C
CLK
C
IDSEL
Notes:
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter include,
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and
ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
A54SX16P DC Specifications (5.0 V PCI Operation)
Parameter
Supply Voltage for Array
Supply Voltage required for Internal Biasing
Supply Voltage for I/Os
Input High Voltage
1
Input Low Voltage
1
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage
2
Input Pin Capacitance
3
CLK Pin Capacitance
IDSEL Pin Capacitance
4
5
V
IN
= 2.7
V
IN
= 0.5
I
OUT
= –2 mA
I
OUT
= 3 mA, 6 mA
2.4
0.55
10
12
8
Condition
Min.
3.0
4.75
4.75
2.0
–0.5
Max.
3.6
5.25
5.25
V
CC
+ 0.5
0.8
70
–70
Units
V
V
V
V
V
µA
µA
V
V
pF
pF
pF
v3.2
1-9
ACTEL [ Actel Corporation ]
