SX-A Family FPGAs
Timing Characteristics
Table 2-14 •
A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions, V
CCA
= 2.25 V
,
V
CCI
= 3.0 V, T
J
= 70°C)
–2 Speed
Parameter
C-Cell Propagation Delays
1
t
PD
Internal Array Module
0.9
1.1
1.2
1.7
ns
Description
–1 Speed
Std. Speed
Min.
Max.
–F Speed
Min. Max. Units
Min. Max. Min. Max.
Predicted Routing Delays
2
t
DC
t
FC
t
RD1
t
RD2
t
RD3
t
RD4
t
RD8
t
RD12
FO = 1 Routing Delay, Direct Connect
FO = 1 Routing Delay, Fast Connect
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
0.1
0.3
0.3
0.5
0.6
0.8
1.4
2
0.1
0.3
0.4
0.5
0.7
0.9
1.5
2.2
0.1
0.4
0.5
0.6
0.8
1
1.8
2.6
0.1
0.6
0.6
0.8
1.1
1.4
2.5
3.6
ns
ns
ns
ns
ns
ns
ns
ns
R-Cell Timing
t
RCO
t
CLR
t
PRESET
t
SUD
t
HD
t
WASYN
t
RECASYN
t
HASYN
t
MPW
Sequential Clock-to-Q
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
Clock Pulse Width
0.7
0.0
1.4
0.4
0.3
1.6
0.7
0.6
0.7
0.8
0.0
1.5
0.4
0.3
1.8
0.8
0.6
0.7
0.9
0.0
1.8
0.5
0.4
2.1
0.9
0.8
0.9
1.2
0.0
2.5
0.7
0.6
2.9
1.3
1.0
1.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Module Propagation Delays
t
INYH
t
INYL
t
INYH
t
INYL
t
INYH
t
INYL
Notes:
1. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
Input Data Pad to Y High 2.5 V LVCMOS
Input Data Pad to Y Low 2.5 V LVCMOS
Input Data Pad to Y High 3.3 V PCI
Input Data Pad to Y Low 3.3 V PCI
Input Data Pad to Y High 3.3 V LVTTL
Input Data Pad to Y Low 3.3 V LVTTL
0.8
1.0
0.6
0.7
0.7
1.0
0.9
1.2
0.6
0.8
0.7
1.1
1.0
1.4
0.7
0.9
0.9
1.3
1.4
1.9
1.0
1.3
1.2
1.8
ns
ns
ns
ns
ns
ns
2 -1 8
v5.3
ACTEL [ Actel Corporation ]
