A54SX16A-2PQG208I (ACTEL) PDF技术资料下载 A54SX16A-2PQG208I 供应信息 IC Datasheet 数据表 (20/108 页)-芯三七

SX-A Family FPGAs

Detailed Specifications

Operating Conditions

Table 2-1 • Absolute Maximum Ratings

Symbol

Parameter

DC Supply Voltage for I/Os

Limits

–0.3 to +6.0

Units

V_CCI

V_CCA

V_I

V

DC Supply Voltage for Arrays

Input Voltage

–0.3 to +3.0

–0.5 to +5.75

–0.5 to + V_CCI+ 0.5

–65 to +150

V

V_O

Output Voltage

V

T_STG

Storage Temperature

°C

Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to

absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the

"Recommended Operating Conditions".

Table 2-2 • Recommended Operating Conditions

Parameter

Commercial

0 to +70

Industrial

–40 to +85

2.25 to 2.75

3.0 to 3.6

Units

Temperature Range

2.5 V Power Supply Range (V_CCAand V_CCI

3.3 V Power Supply Range (V_CCI

5 V Power Supply Range (V_CCI

°C

V

)

2.25 to 2.75

3.0 to 3.6

)

V

)

4.75 to 5.25

V

Typical SX-A Standby Current

Table 2-3 • Typical Standby Current for SX-A at 25°C with V_CCA= 2.5 V

Product

V

_CCI= 2.5 V

0.8 mA

V_CCI= 3.3 V

1.0 mA

V_CCI= 5 V

A54SX08A

A54SX16A

A54SX32A

A54SX72A

2.9 mA

3.0 mA

4.5 mA

0.8 mA

1.0 mA

0.9 mA

1.0 mA

3.6 mA

3.8 mA

Table 2-4 • Supply Voltages

V_CCA

2. 5 V

2.5 V

V_CCI

*

Maximum Input Tolerance

Maximum Output Drive

2.5 V

3.3 V

5 V

5.75 V

2.7 V

3.6 V

5.25 V

Note: *3.3 V PCI is not 5 V tolerant due to the clamp diode, but instead is 3.3 V tolerant.

v5.3

2-1

SX-A Family FPGAs

Electrical Specifications

Table 2-5 • 3.3 V LVTTL and 5 V TTL Electrical Specifications

Commercial

Industrial

Symbol

Parameter

Min.

(I_OH= –1 mA) 0.9 V_CCI

Max.

Min.

Max.

Units

V_OH

V_CCI= Minimum

V_I= V_IHor V_IL

0.9 V_CCI

V

V_CCI= Minimum

V_I= V_IHor V_IL

(I_OH= –8 mA)

(I_OL= 1 mA)

(I_OL= 12 mA)

2.4

V

V_OL

V_CCI= Minimum

V_I= V_IHor V_IL

0.4

V_CCI= Minimum

V_I= V_IHor V_IL

V_IL

Input Low Voltage

Input High Voltage

0.8

5.75

10

0.8

5.75

10

V

V_IH

2.0

–10

2.0

–10

I_IL/I_IH

I_OZ

Input Leakage Current, V_IN= V_CCIor GND

Tristate Output Leakage Current

Input Transition Time t_R, t_F

I/O Capacitance

µA

ns

10

t_R, t_F

C_IO

I_CC

10

pF

mA

Standby Current

10

20

IV Curve* Can be derived from the IBIS model on the web.

Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.

Table 2-6 • 2.5 V LVCMOS2 Electrical Specifications

Commercial

Industrial

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

V_OH

V_DD= MIN,

V_I= V_IHor V_IL

(I_OH= –100 μA)

(I_OH= –1 mA)

(I_OH=–-2 mA)

(I_OL= 100 μA)

(I_OL= 1 mA)

2.1

V

V_DD= MIN,

V_I= V_IHor V_IL

2.0

1.7

2.0

1.7

V

V_DD= MIN,

V_I= V_IHor V_IL

V_OL

V_DD= MIN,

V_I= V_IHor V_IL

0.2

0.4

0.7

0.2

0.4

0.7

V_DD= MIN,

V_I= V_IHor V_IL

V_DD= MIN,

(I_OL= 2 mA)

V_I= V_IHor V_IL

V_IL

Input Low Voltage, V_OUT≤ V_VOL(max)

Input High Voltage, V_OUT≥ V_VOH(min)

Input Leakage Current, V_IN= V_CCIor GND

Tristate Output Leakage Current, V_OUT= V_CCIor GND

Input Transition Time t_R, t_F

-0.3

1.7

0.7

5.75

10

-0.3

1.7

0.7

5.75

10

V

V_IH

I_IL/I_IH

I_OZ

–10

µA

ns

10

t_R, t_F

C_IO

I_CC

10

I/O Capacitance

10

pF

mA

Standby Current

10

20

IV Curve* Can be derived from the IBIS model on the web.

Note: *The IBIS model can be found at http://www.actel.com/download/ibis/default.aspx.

2-2

v5.3

SX-A Family FPGAs

PCI Compliance for the SX-A Family

The SX-A family supports 3.3 V and 5 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1.

Table 2-7 • DC Specifications (5 V PCI Operation)

Symbol

V_CCA

V_CCI

V_IH

Parameter

Supply Voltage for Array

Condition

Min.

2.25

4.75

2.0

–0.5

–

Max.

2.75

5.25

5.75

0.8

Units

V

Supply Voltage for I/Os

Input High Voltage

V

V_IL

Input Low Voltage

V

I_IH

Input High Leakage Current¹

Input Low Leakage Current¹

Output High Voltage

Output Low Voltage²

Input Pin Capacitance³

CLK Pin Capacitance

V_IN= 2.7

70

µA

V

I_IL

V_IN= 0.5

–

–70

–

V_OH

V_OL

I_OUT= –2 mA

I_OUT= 3 mA, 6 mA

2.4

–

0.55

10

V

C_IN

–

pF

C_CLK

Notes:

5

12

1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter includes

FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and

ACK64#.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).

v5.3

2-3

SX-A Family FPGAs

Table 2-8 • AC Specifications (5 V PCI Operation)

Symbol

Parameter

Condition

0 < V_OUT≤ 1.4 ¹

1.4 ≤ V_OUT< 2.4 ^{1, 2}

Min.

Max.

Units

mA

–

I_OH(AC)

Switching Current High

–44

–

(–44 + (V_OUT– 1.4)/0.024)

–

1, 3

3.1 < V_OUT< V_CCI

EQ 2-1 on

page 2-5

(Test Point)

V

_OUT= 3.1 ³

–

–142

mA

–

I_OL(AC)

Switching Current Low

V_OUT≥ 2.2 ¹

95

–

2.2 > V_OUT> 0.55 ¹

0.71 > V_OUT> 0 ^{1, 3}

(V_OUT/0.023)

–

EQ 2-2 on

page 2-5

(Test Point)

V_OUT= 0.71 ³

–

206

–

mA

I_CL

Low Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–5 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

slew_R

slew_F

Notes:

0.4 V to 2.4 V load ⁴

2.4 V to 0.4 V load ⁴

1

5

V/ns

5

1. Refer to the V/I curves in Figure 2-1 on page 2-5. Switching current characteristics for REQ# and GNT# are permitted to be one half

of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,

which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,

which are open drain outputs.

2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than

toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.

3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A

and B) are provided with the respective diagrams in Figure 2-1 on page 2-5. The equation defined maximum should be met by

design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.

4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any

point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter

with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum

parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not

required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge

rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and

should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs.

1/2 in. max.

Output

Buffer

50 pF

2-4

v5.3

SX-A Family FPGAs

Figure 2-1 shows the 5 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.

200.0

I

MAX Spec

OL

I

OL

150.0

100.0

50.0

I

MIN Spec

3.5

OL

0.0

0

0.5

1

1.5

2

2.5

3

4

4.5

I

5

5.5

6

–50.0

–100.0

–150.0

–200.0

I

MIN Spec

OH

MAX Spec

OH

I

OH

Voltage Out (V)

Figure 2-1 • 5 V PCI V/I Curve for SX-A Family

_OH= 11.9 * (V_OUT– 5.25) * (V_OUT+ 2.45)

I

I_OL= 78.5 * V_OUT* (4.4 – V_OUT

for 0V < V_OUT< 0.71V

)

for V_CCI> V_OUT> 3.1V

EQ 2-1

EQ 2-2

Table 2-9 • DC Specifications (3.3 V PCI Operation)

Symbol

V_CCA

V_CCI

V_IH

Parameter

Condition

Min.

Max.

Units

V

Supply Voltage for Array

Supply Voltage for I/Os

Input High Voltage

Input Low Voltage

Input Pull-up Voltage¹

Input Leakage Current²

Output High Voltage

Output Low Voltage

Input Pin Capacitance³

CLK Pin Capacitance

2.25

3.0

2.75

3.6

V

0.5V_CCI

–0.5

V_CCI+ 0.5

0.3V_CCI

–

V

V_IL

V

I_IPU

0.7V_CCI

–10

V

I_IL

0 < V_IN< V_CCI

I_OUT= –500 µA

I_OUT= 1,500 µA

+10

μA

V

V_OH

V_OL

0.9V_CCI

–

0.1V_CCI

10

V

C_IN

–

pF

C_CLK

Notes:

5

12

1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a

floated network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications

sensitive to static power utilization.

2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.

3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).

v5.3

2-5

SX-A Family FPGAs

Table 2-10 • AC Specifications (3.3 V PCI Operation)

Symbol

Parameter

Condition

Min.

Max.

Units

mA

–

1

I_OH(AC)

Switching Current High

0 < V_OUT≤ 0.3V_CCI

–12V_CCI

–

1

0.3V_CCI≤ V_OUT< 0.9V_CCI

(–17.1(V_CCI– V_OUT))

–

1, 2

0.7V_CCI< V_OUT< V_CCI

EQ 2-3 on

page 2-7

2

(Test Point)

V

_OUT= 0.7V_CC

–

–32V_CCI

mA

–

1

I_OL(AC)

Switching Current Low

V_CCI> V_OUT≥ 0.6V_CCI

16V_CCI

–

1

0.6V_CCI> V_OUT> 0.1V_CCI

0.18V_CCI> V_OUT> 0 ^{1, 2}

(26.7V_OUT

)

–

EQ 2-4 on

page 2-7

2

(Test Point)

V_OUT= 0.18V_CC

–

38V_CCI

mA

I_CL

Low Clamp Current

High Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

–3 < V_IN≤ –1

–25 + (V_IN+ 1)/0.015

–

4

I_CH

V_CCI+ 4 > V_IN≥ V_CCI+ 1

0.2V_CCI- 0.6V_CCIload ³

0.6V_CCI- 0.2V_CCIload ³

25 + (V_IN– V_CCI– 1)/0.015

mA

slew_R

slew_F

Notes:

1

V/ns

1. Refer to the V/I curves in Figure 2-2 on page 2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half

of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,

which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,

which are open drain outputs.

2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C

and D) are provided with the respective diagrams in Figure 2-2 on page 2-7. The equation defined maximum should be met by

design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any

point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter

with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and

minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain

outputs.

1/2 in. max.

Output

Buffer

10 pF

1 k/25 Ω

Output

Buffer

10 pF

2-6

v5.3

SX-A Family FPGAs

Figure 2-2 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family.

150.0

I

MAX Spec

OL

I

OL

100.0

50.0

I

MIN Spec

2.5

OL

0.0

0

0.5

MIN Spec

1

1.5

2

3

3.5

4

–50.0

–100.0

–150.0

I

OH

I

MAX Spec

I

OH

Voltage Out (V)

Figure 2-2 • 3.3 V PCI V/I Curve for SX-A Family

I_OH= (98.0/V_CCI) * (V_OUT– V_CCI) * (V_OUT+ 0.4V_CCI

)

I_OL= (256/V_CCI) * V_OUT* (V_CCI– V_OUT

)

for 0.7 V_CCI< V_OUT< V_CCI

for 0V < V_OUT< 0.18 V_CCI

EQ 2-3

EQ 2-4

v5.3

2-7

SX-A Family FPGAs

Power Dissipation

A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during

operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature,

the operating current, and the system's ability to dissipate heat.

A complete power evaluation should be performed early in the design process to help identify potential heat-related

problems in the system and to prevent the system from exceeding the device’s maximum allowed junction

temperature.

The actual power dissipated by most applications is significantly lower than the power the package can dissipate.

However, a thermal analysis should be performed for all projects. To perform a power evaluation, follow these steps:

1. Estimate the power consumption of the application.

2. Calculate the maximum power allowed for the device and package.

3. Compare the estimated power and maximum power values.

Estimating Power Dissipation

The total power dissipation for the SX-A family is the sum of the DC power dissipation and the AC power dissipation:

P

_Total= P_DC+ P_AC

EQ 2-5

DC Power Dissipation

The power due to standby current is typically a small component of the overall power. An estimation of DC power

dissipation under typical conditions is given by:

P_DC= I_Standby* V_CCA

EQ 2-6

Note: For other combinations of temperature and voltage settings, refer to the eX, SX-A and RT54SX-S Power

Calculator.

AC Power Dissipation

The power dissipation of the SX-A family is usually dominated by the dynamic power dissipation. Dynamic power

dissipation is a function of frequency, equivalent capacitance, and power supply voltage. The AC power dissipation is

defined as follows:

P_AC= P_C-cells+ P_R-cells+ P_CLKA+ P_CLKB+ P_HCLK+ P_{Output Buffer}+ P_{Input Buffer}

EQ 2-7

or:

V_CCA²* [(m * C_EQCM* fm)_C-cells+ (m * C_EQSM* fm)_R-cells+ (n * C_EQI* f_n)_{Input Buffer}+ (p * (C_EQO+ C_L) * f_p)_{Output Buffer}

P_AC

=

+ (0.5 * (q₁* C_EQCR* f_q1) + (r₁* f_{q1 CLKA}

))

+ (0.5 * (q₂* C_EQCR* f_q2)+ (r₂* f_q2))_CLKB+ (0.5 * (s₁* C_EQHV* f_s1) +

(C_EQHF* f_s1))_HCLK

]

EQ 2-8

2-8

v5.3

SX-A Family FPGAs

Where:

C_EQCM= Equivalent capacitance of combinatorial modules

(C-cells) in pF

C_EQSM= Equivalent capacitance of sequential modules (R-Cells) in pF

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in pF

C_EQCR= Equivalent capacitance of CLKA/B in pF

C_EQHV= Variable capacitance of HCLK in pF

C_EQHF= Fixed capacitance of HCLK in pF

C_{L =}Output lead capacitance in pF

f_m= Average logic module switching rate in MHz

f_n= Average input buffer switching rate in MHz

f_p= Average output buffer switching rate in MHz

f_q1= Average CLKA rate in MHz

f

_q2= Average CLKB rate in MHz

f_s1= Average HCLK rate in MHz

m = Number of logic modules switching at fm

n = Number of input buffers switching at fn

p = Number of output buffers switching at fp

q₁= Number of clock loads on CLKA

q₂= Number of clock loads on CLKB

r₁= Fixed capacitance due to CLKA

r₂= Fixed capacitance due to CLKB

s_{1 =}Number of clock loads on HCLK

x = Number of I/Os at logic low

y = Number of I/Os at logic high

Table 2-11 • CEQ Values for SX-A Devices

A54SX08A

1.70 pF

1.50 pF

1.30 pF

7.40 pF

1.05 pF

0.85 pF

A54SX16A

2.00 pF

1.50 pF

1.30 pF

7.40 pF

1.05 pF

0.85 pF

A54SX32A

2.00 pF

1.30 pF

7.40 pF

1.05 pF

0.85 pF

A54SX72A

1.80 pF

1.50 pF

1.30 pF

7.40 pF

1.05 pF

0.85 pF

Combinatorial modules (C_EQCM

Sequential modules (C_EQCM

Input buffers (C_EQI

Output buffers (C_EQO

)

Routed array clocks (C_EQCR

)

Dedicated array clocks

–

variable

(C_EQHV

Dedicated array clocks – fixed (C_EQHF

Routed array clock A (r₁)

)

30.00 pF

35.00 pF

55.00 pF

50.00 pF

110.00 pF

90.00 pF

240.00 pF

310.00 pF

v5.3

2-9

SX-A Family FPGAs

Guidelines for Estimating Power

The following guidelines are meant to represent worst-case scenarios; they can be generally used to predict the upper

limits of power dissipation:

Logic Modules (m) = 20% of modules

Inputs Switching (n) = Number inputs/4

Outputs Switching (p) = Number of outputs/4

CLKA Loads (q1) = 20% of R-cells

CLKB Loads (q2) = 20% of R-cells

Load Capacitance (CL) = 35 pF

Average Logic Module Switching Rate (fm) = f/10

Average Input Switching Rate (fn) =f/5

Average Output Switching Rate (fp) = f/10

Average CLKA Rate (fq1) = f/2

Average CLKB Rate (fq2) = f/2

Average HCLK Rate (fs1) = f

HCLK loads (s1) = 20% of R-cells

To assist customers in estimating the power dissipations of their designs, Actel has published the eX, SX-A and RT54SX-S

Power Calculator worksheet.

2-10

v5.3

SX-A Family FPGAs

Thermal Characteristics

Introduction

The temperature variable in Actel Designer software refers to the junction temperature, not the ambient, case, or

board temperatures. This is an important distinction because dynamic and static power consumption will cause the

chip's junction to be higher than the ambient, case, or board temperatures. EQ 2-9 and EQ 2-10 give the relationship

between thermal resistance, temperature gradient and power.

T_J– T_A

θ_JA= ----------------

P

EQ 2-9

T_C– T_A

θ_JA= -----------------

P

EQ 2-10

Where:

θ

=

Junction-to-air thermal resistance

Junction-to-case thermal resistance

JA

JC

T_J= Junction temperature

T_A= Ambient temperature

T_C= Ambient temperature

P

= total power dissipated by the device

Table 2-12 • Package Thermal Characteristics

θ_JA

1.0 m/s

2.5 m/s

Package Type

Count

θ_JC

14

11

8

Still Air 200 ft./min. 500 ft./min.

Units

°C/W

Thin Quad Flat Pack (TQFP)

100

144

176

208

329

144

256

484

33.5

24.7

26.1

16.2

17.1

26.9

26.6

18

27.4

28

25

Thin Quad Flat Pack (TQFP)

25.7

18

Thin Quad Flat Pack (TQFP)

19.9

22.5

13.3

13.8

22.9

22.8

14.7

Plastic Quad Flat Pack (PQFP)¹

Plastic Quad Flat Pack (PQFP) with Heat Spreader²

Plastic Ball Grid Array (PBGA)

Fine Pitch Ball Grid Array (FBGA)

20.8

11.9

12.8

21.5

13.6

3.8

3

3.8

3.2

Notes:

1. The A54SX08A PQ208 has no heat spreader.

2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.

v5.3

2-11

SX-A Family FPGAs

Theta-JA

Junction-to-ambient thermal resistance (θ ) is determined under standard conditions specified by JESD-51 series but

JA

has little relevance in actual performance of the product in real application. It should be employed with caution but is

useful for comparing the thermal performance of one package to another.

A sample calculation to estimate the absolute maximum power dissipation allowed (worst case) for a 329-pin PBGA

package at still air is as follows. i.e.:

θ_JA= 17.1°C/W is taken from Table 2-12 on page 2-11

T_A= 125°C is the maximum limit of ambient (from the datasheet)

Max Junction Temp – Max. Ambient Temp

150°C – 125°C

Max. Allowed Power = ----------------------------------------------------------------------------------------------------------- = --------------------------------------- = 1.46 W

θ_JA17.1°C/W

EQ 2-11

The device's power consumption must be lower than the calculated maximum power dissipation by the package.

The power consumption of a device can be calculated using the Actel power calculator. If the power consumption is

higher than the device's maximum allowable power dissipation, then a heat sink can be attached on top of the case or

the airflow inside the system must be increased.

Theta-JC

Junction-to-case thermal resistance (θ ) measures the ability of a device to dissipate heat from the surface of the chip

JC

to the top or bottom surface of the package. It is applicable for packages used with external heat sinks and only

applies to situations where all or nearly all of the heat is dissipated through the surface in consideration. If the power

consumption is higher than the calculated maximum power dissipation of the package, then a heat sink is required.

Calculation for Heat Sink

For example, in a design implemented in a FG484 package, the power consumption value using the power calculator is

3.00 W. The user-dependent data T_Jand T_Aare given as follows:

=

T_J

110°C

70°C

T_A

From the datasheet:

θ

=

18.0°C/W

3.2 °C/W

JA

JC

Max Junction Temp – Max. Ambient Temp

110°C – 70°C

P = ----------------------------------------------------------------------------------------------------------- = ------------------------------------ = 2.22 W

θ_JA18.0°C/W

EQ 2-12

The 2.22 W power is less than then required 3.00 W; therefore, the design requires a heat sink or the airflow where the

device is mounted should be increased. The design's junction-to-air thermal resistance requirement can be estimated

by:

Max Junction Temp – Max. Ambient Temp

110°C – 70°C

3.00 W

θ_JA= ----------------------------------------------------------------------------------------------------------- = ------------------------------------ = 13.33°C/W

P

EQ 2-13

2-12

v5.3

SX-A Family FPGAs

To determine the heat sink's thermal performance, use the following equation:

θ_JA(TOTAL)= θ_JC+ θ_CS+ θ_SA

EQ 2-14

where:

θ_CS

=

0.37°C/W

thermal resistance of the interface material between the case and the heat

sink, usually provided by the thermal interface manufacturer

θ_SA

=

thermal resistance of the heat sink in °C/W

θ_SA= θ_JA(TOTAL)– θ_JC– θ_CS

EQ 2-15

θ_SA= 13.33°C/W – 3.20°C/W – 0.37°C/W

θ_SA= 9.76°C/W

A heat sink with a thermal resistance of 9.76°C/W or better should be used. Thermal resistance of heat sinks is a

function of airflow. The heat sink performance can be significantly improved with the presence of airflow.

Carefully estimating thermal resistance is important in the long-term reliability of an Actel FPGA. Design engineers

should always correlate the power consumption of the device with the maximum allowable power dissipation of the

package selected for that device, using the provided thermal resistance data.

Note: The values may vary depending on the application.

v5.3

2-13

SX-A Family FPGAs

SX-A Timing Model

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

Combinatorial

Cell

t

= 0.3 ns

= 0.5 ns

I/O Module

RD1

RD2

t

= 0.6 ns

INYH

t

= 3.9 ns

DHL

t

= 1.1 ns

PD

t

= 0.3 ns

RD1

= 0.9 ns

RD4

= 1.5 ns

RD8

I/O Module

t

= 3.9 ns

Register

Cell

DHL

D

Q

t

RD1

= 0.8 ns

= 0.0 ns

= 0.3 ns

SUD

HD

t

= 1.5 ns

ENZL

Routed

Clock

t

= 3.0 ns

RCKH

t

= 0.8 ns

(100% Load)

RCO

I/O Module

= 3.9 ns

DHL

Register

Cell

I/O Module

t

= 0.6 ns

INYH

D

Q

t

RD1

= 0.8 ns

= 0.0 ns

= 0.3 ns

SUD

= 1.5 ns

ENZL

HD

Hardwired

Clock

t

RCO

= 1.8 ns

= 0.8 ns

HCKH

Note: *Values shown for A54SX72A, –2, worst-case commercial conditions at 5 V PCI with standard place-and-route.

Figure 2-3 • SX-A Timing Model

Sample Path Calculations

Hardwired Clock

Routed Clock

External Setup

= (t_INYH+ t_RD1+ t_SUD) – t_HCKH

= 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns

External Setup

= (t_INYH+ t_RD1+ t_SUD) – t_RCKH

= 0.6 + 0.3 + 0.8 - 3.0 = –1.3 ns

Clock-to-Out (Pad-to-Pad) = t_HCKH+ t_RCO+ t_RD1+ t_DHL

= 1.8 + 0.8 + 0.3 + 3.9 = 6.8 ns

Clock-to-Out (Pad-to-Pad) = t_RCKH+ t_RCO+ t_RD1+ t_DHL

= 3.0 + 0.8 + 0.3 + 3.9 = 8.0 ns

2-14

v5.3

SX-A Family FPGAs

Output Buffer Delays

E

D

PAD To AC Test Loads (shown below)

TRIBUFF

V_CC

In

50% 50%

V_OH

En

GND

1.5 V

En

Out

50%

GND

90%

GND

10%

50%

V_CC

50%

1.5 V

V_OL

Out

1.5 V

Out

GND

1.5 V

V_OL

t_DLH

t_ENHZ

t_ENZH

t_ENZL

t_ENLZ

Figure 2-4 • Output Buffer Delays

AC Test Loads

Load 1

(Used to measure

propagation delay)

Load 3

(Used to measure disable delays)

Load 2

(Used to measure enable delays)

V_CC

GND

To the Output

Under Test

t

R to V_CCfor

R to V_CCfor PZL

R to GND for^Pt^Z_P^L_ZH

R to GND for PZH

R = 1 kΩ

t

35 pF

To the Output

Under Test

To the Output

Under Test

R = 1 kΩ

35 pF

5 pF

Figure 2-5 • AC Test Loads

v5.3

2-15

SX-A Family FPGAs

Input Buffer Delays

C-Cell Delays

S

A

B

Y

PAD

INBUF

V_CC

GND

50%

V_CC

S, A, or B 50%

3 V

50%

Out

GND

t_PD

50%

In

1.5 V 1.5 V

V_CC

0 V

t_PD

V_CC

50%

Out

GND

50%

Out

GND

t_PD

50%

t_PD

t_INY

Figure 2-6 • Input Buffer Delays

Figure 2-7 • C-Cell Delays

Cell Timing Characteristics

D

Q

PRESET

CLR

CLK

(Positive Edge Triggered)

t_HD

D

t_SUD

CLK

t_HP

t_HPWH

t_RPWH

t_HPWL

t_RPWL

t_RCO

Q

t_CLR

t_WASYN

t_PRESET

CLR

PRESET

Figure 2-8 • Flip-Flops

2-16

v5.3

SX-A Family FPGAs

Long Tracks

Timing Characteristics

Some nets in the design use long tracks. Long tracks are

special routing resources that span multiple rows,

columns, or modules. Long tracks employ three to five

antifuse connections. This increases capacitance and

resistance, resulting in longer net delays for macros

connected to long tracks. Typically, up to 6 percent of

nets in a fully utilized device require long tracks. Long

tracks contribute approximately 4 ns to 8.4 ns delay. This

additional delay is represented statistically in higher

fanout routing delays.

Timing characteristics for SX-A devices fall into three

categories: family-dependent, device-dependent, and

design-dependent. The input and output buffer

characteristics are common to all SX-A family members.

Internal routing delays are device-dependent. Design

dependency means actual delays are not determined

until after placement and routing of the user’s design are

complete. The timing characteristics listed in this

datasheet represent sample timing numbers of the SX-A

devices. Design-specific delay values may be determined

by using Timer or performing simulation after successful

place-and-route with the Designer software.

Timing Derating

SX-A devices are manufactured with a CMOS process.

Therefore, device performance varies according to

temperature, voltage, and process changes. Minimum

timing parameters reflect maximum operating voltage,

minimum operating temperature, and best-case

processing. Maximum timing parameters reflect

minimum operating voltage, maximum operating

temperature, and worst-case processing.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets,

which are used for initial design performance evaluation.

Critical net delays can then be applied to the most

timing-critical paths. Critical nets are determined by net

property assignment prior to placement and routing. Up

to 6 percent of the nets in a design may be designated as

critical, while 90 percent of the nets in a design are

typical.

Temperature and Voltage Derating Factors

Table 2-13 • Temperature and Voltage Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, V_CCA= 2.25 V)

Junction Temperature (T_J)

V_CCA

–55°C

0.79

–40°C

0.80

0°C

0.87

0.82

0.75

25°C

0.89

0.83

0.77

70°C

1.00

0.94

0.87

85°C

1.04

0.97

0.90

125°C

1.14

2.250 V

2.500 V

2.750 V

0.74

0.75

1.07

0.68

0.69

0.99

v5.3

2-17

SX-A Family FPGAs

Timing Characteristics

Table 2-14 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–2 Speed

–1 Speed

Std. Speed

–F Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

C-Cell Propagation Delays¹

t_PD

Internal Array Module

0.9

1.1

1.2

1.7

ns

Predicted Routing Delays²

t_DC

FO = 1 Routing Delay, Direct Connect

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.1

0.3

0.5

0.6

0.8

1.4

2

0.1

0.3

0.4

0.5

0.7

0.9

1.5

2.2

0.1

0.4

0.5

0.6

0.8

1

0.1

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_FC

t_RD1

t_RD2

FO = 2 Routing Delay

t_RD3

FO = 3 Routing Delay

t_RD4

FO = 4 Routing Delay

t_RD8

FO = 8 Routing Delay

1.8

2.6

t_RD12

R-Cell Timing

t_RCO

FO = 12 Routing Delay

Sequential Clock-to-Q

0.7

0.6

0.7

0.8

0.6

0.7

0.9

0.8

0.9

1.3

1.0

1.2

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Hold Time

Clock Pulse Width

t_PRESET

t_SUD

0.7

0.0

1.4

0.4

0.3

1.6

0.8

0.0

1.5

0.4

0.3

1.8

0.9

0.0

1.8

0.5

0.4

2.1

1.2

0.0

2.5

0.7

0.6

2.9

t_HD

t_WASYN

t_RECASYN

t_HASYN

t_MPW

Input Module Propagation Delays

t_INYHInput Data Pad to Y High 2.5 V LVCMOS

t_INYL

t_INYH

t_INYL

t_INYH

t_INYL

0.8

1.0

0.6

0.7

1.0

0.9

1.2

0.6

0.8

0.7

1.1

1.0

1.4

0.7

0.9

1.3

1.4

1.9

1.0

1.3

1.2

1.8

ns

Input Data Pad to Y Low 2.5 V LVCMOS

Input Data Pad to Y High 3.3 V PCI

Input Data Pad to Y Low 3.3 V PCI

Input Data Pad to Y High 3.3 V LVTTL

Input Data Pad to Y Low 3.3 V LVTTL

Notes:

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2-18

v5.3

SX-A Family FPGAs

–F Speed

Table 2-14 • A54SX08A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–2 Speed

–1 Speed

Std. Speed

Parameter

t_INYH

Description

Input Data Pad to Y High 5 V PCI

Input Data Pad to Y Low 5 V PCI

Input Data Pad to Y High 5 V TTL

Input Data Pad to Y Low 5 V TTL

Min. Max. Min. Max. Min. Max. Min. Max. Units

0.5

0.8

0.5

0.8

0.6

0.9

0.6

0.9

0.7

1.1

0.7

1.1

0.9

1.5

0.9

1.5

ns

t_INYL

t_INYH

t_INYL

Input Module Predicted Routing Delays²

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

0.3

0.5

0.6

0.8

1.4

2

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_IRD2

t_IRD3

t_IRD4

t_IRD8

1.8

2.6

t_IRD12

Notes:

1. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5.3

2-19

SX-A Family FPGAs

Table 2-15 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.25 V, T_J= 70°C)

–2 Speed –1 Speed Std. Speed

Min. Max. Min. Max. Min. Max. Min. Max. Units

–F Speed

Parameter

Description

Dedicated (Hardwired) Array Clock Networks

t_HCKH

t_HCKL

Input Low to High

(Pad to R-cell Input)

1.4

1.3

1.6

1.5

1.8

1.7

2.6

2.4

ns

Input High to Low

(Pad to R-cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.6

1.8

2.1

2.9

ns

0.4

0.5

0.7

ns

Minimum Period

3.2

3.6

4.2

5.8

ns

f_HMAX

Maximum Frequency

313

278

238

172

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

1.0

1.1

1.0

1.1

1.3

1.1

1.2

1.1

1.2

1.5

1.3

1.4

1.3

1.4

1.7

1.8

2.0

1.8

2.0

2.4

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.6

1.8

2.1

2.9

ns

t_RPWL

t_RCKSW

0.7

0.9

0.8

1.0

0.9

1.2

1.3

1.7

2-20

v5.3

SX-A Family FPGAs

–F Speed

Table 2-16 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–2 Speed –1 Speed

Std. Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

t_HCKH

t_HCKL

Input Low to High

(Pad to R-cell Input)

1.3

1.1

1.5

1.3

1.7

1.5

2.6

2.2

ns

Input High to Low

(Pad to R-cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.6

1.8

2.1

2.9

ns

0.4

0.5

0.8

ns

Minimum Period

3.2

3.6

4.2

5.8

ns

f_HMAX

Maximum Frequency

313

278

238

172

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

0.8

1.1

0.8

1.1

1.2

0.9

1.2

0.9

1.2

1.3

1.1

1.4

1.1

1.4

1.6

1.5

2

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

1.5

2

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

1.9

2.2

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.6

1.8

2.1

2.9

ns

t_RPWL

t_RCKSW

0.7

0.8

0.9

1.1

1.3

1.5

v5.3

2-21

SX-A Family FPGAs

Table 2-17 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–2 Speed –1 Speed Std. Speed

Min. Max. Min. Max. Min. Max. Min. Max. Units

–F Speed

Parameter

Description

Dedicated (Hardwired) Array Clock Networks

t_HCKH

t_HCKL

Input Low to High

(Pad to R-cell Input)

1.2

1.0

1.3

1.2

1.5

1.4

2.3

2.0

ns

Input High to Low

(Pad to R-cell Input)

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.6

1.8

2.1

2.9

ns

0.4

0.5

0.8

ns

Minimum Period

3.2

3.6

4.2

5.8

ns

f_HMAX

Maximum Frequency

313

278

238

172

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

0.9

1.5

0.9

1.5

1.1

1.6

1.0

1.7

1.0

1.7

1.3

1.8

1.2

2.0

1.2

2.0

1.5

2.1

1.7

2.7

1.7

2.7

2.1

2.9

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.6

1.8

2.1

2.9

ns

t_RPWL

t_RCKSW

0.8

0.9

1.0

1.1

1.2

1.5

1.7

2-22

v5.3

SX-A Family FPGAs

–F Speed

Table 2-18 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.3 V, T_J= 70°C)

–2 Speed –1 Speed

Std. Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

2.5 V LVCMOS Output Module Timing^1,2

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

3.9

3.0

4.4

3.4

5.2

3.9

7.2

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

13.3

2.8

15.1

3.2

17.7

3.7

24.8

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

13.7

3.9

15.5

4.4

18.2

5.2

25.5

7.2

Enable-to-Pad, L to Z

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

3.0

3.4

3.9

5.5

3

d_TLH

Delta Low to High

0.037

0.017

0.06

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

3

d_THL

Delta High to Low

3

d_THLS

Delta High to Low—low slew

Note:

1. Delays based on 35 pF loading.

2. The equivalent I/O Attribute Editor settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

v5.3

2-23

SX-A Family FPGAs

Table 2-19 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–2 Speed –1 Speed

Min. Max. Min. Max. Min. Max. Min. Max. Units

Std. Speed

–F Speed

Parameter

Description

3.3 V PCI Output Module Timing¹

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

2.2

2.3

2.4

2.6

2.9

3.1

4.0

4.3

3.1

4.0

5.3

4.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.7

1.9

2.2

2.4

2.9

2.8

3.2

3.8

2.3

2.6

3.1

2

d_TLH

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

2

d_THL

Delta High to Low

3.3 V LVTTL Output Module Timing³

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

3.0

3.4

3.3

4.0

3.9

5.6

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

10.4

2.6

11.8

2.9

13.8

3.4

19.3

4.8

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

18.9

3

21.3

3.4

25.4

4

34.9

5.6

Enable-to-Pad, L to Z

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

3

3.3

3.9

5.5

2

d_TLH

Delta Low to High

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

2

d_THL

Delta High to Low

2

d_THLS

Delta High to Low—low slew

Notes:

1. Delays based on 10 pF loading and 25 Ω resistance.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

3. Delays based on 35 pF loading.

2-24

v5.3

SX-A Family FPGAs

–F Speed

Table 2-20 • A54SX08A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–2 Speed –1 Speed Std. Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

5 V PCI Output Module Timing¹

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

2.4

3.2

2.8

3.6

3.2

4.2

4.5

5.9

2.8

4.5

6.4

5.9

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.5

1.7

2.0

2.4

2.8

3.2

3.5

3.9

4.6

3.2

3.6

4.2

2

d_TLH

0.016

0.03

0.02

0.032

0.022

0.04

0.032 ns/pF

0.052 ns/pF

2

d_THL

Delta High to Low

5 V TTL Output Module Timing³

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

2.4

3.2

2.8

3.6

3.2

4.2

4.5

5.9

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

d_TLH

7.6

8.6

10.1

3.2

14.2

4.5

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

8.4

9.5

11.0

3.2

15.4

4.5

2.4

2.8

Enable-to-Pad, L to Z

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

3.2

3.6

4.2

5.9

Delta Low to High

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

d_THL

Delta High to Low

d_THLS

Notes:

Delta High to Low—low slew

1. Delays based on 50 pF loading.

2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

3. Delays based on 35 pF loading.

v5.3

2-25

SX-A Family FPGAs

Table 2-21 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–3 Speed¹

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

–2 Speed

–1 Speed

Std. Speed

–F Speed

Parameter

C-Cell Propagation Delays²

t_PDInternal Array Module

Predicted Routing Delays³

Description

0.9

0.1

1.0

0.1

1.2

0.1

1.4

0.1

1.9

0.1

ns

t_DC

FO

= 1 Routing Delay, Direct

Connect

t_FC

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.6

0.8

1.4

2

0.3

0.4

0.5

0.7

0.9

1.5

2.2

0.4

0.5

0.6

0.8

1

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

1.8

2.6

FO = 12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.6

0.5

0.7

0.6

0.8

0.6

0.8

0.9

0.8

1.0

1.3

1.0

1.4

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Clock Minimum Pulse Width

t_PRESET

t_SUD

0.7

0.0

1.3

0.3

1.4

0.8

0.0

1.5

0.4

0.3

1.7

0.9

0.0

1.6

0.4

0.3

1.9

1.0

0.0

1.9

0.5

0.4

2.2

1.4

0.0

2.7

0.7

0.6

3.0

t_HD

t_WASYN

t_RECASYN

t_HASYN

t_MPW

Input Module Propagation Delays

t_INYHInput Data Pad to Y High 2.5 V

0.5

0.8

0.6

0.9

0.7

1.0

0.8

1.1

1.6

ns

LVCMOS

t_INYL

Input Data Pad to Y Low 2.5 V

LVCMOS

t_INYH

t_INYL

t_INYH

Input Data Pad to Y High 3.3 V PCI

Input Data Pad to Y Low 3.3 V PCI

0.5

0.7

0.6

0.8

0.7

0.6

0.9

0.8

0.7

1.0

1.4

ns

Input Data Pad to Y High 3.3 V

LVTTL

t_INYL

Input Data Pad to Y Low 3.3 V LVTTL

0.9

1.1

1.2

1.4

2.0

ns

Notes:

1. All –3 speed grades have been discontinued.

2. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2-26

v5.3

SX-A Family FPGAs

Std. Speed –F Speed

Table 2-21 • A54SX16A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–3 Speed¹

–2 Speed

–1 Speed

Parameter

t_INYH

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Data Pad to Y High 5 V PCI

Input Data Pad to Y Low 5 V PCI

Input Data Pad to Y High 5 V TTL

Input Data Pad to Y Low 5 V TTL

0.5

0.7

0.5

0.7

0.5

0.8

0.5

0.8

0.6

0.9

0.6

0.9

0.7

1.1

0.7

1.1

0.9

1.5

0.9

1.5

ns

t_INYL

t_INYH

t_INYL

Input Module Predicted Routing Delays²

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.6

0.8

1.4

2.0

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1.0

0.8

2.6

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_IRD2

t_IRD3

t_IRD4

t_IRD8

t_IRD12

Notes:

1. All –3 speed grades have been discontinued.

2. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5.3

2-27

SX-A Family FPGAs

Table 2-22 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.25 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.2

1.4

1.6

1.8

2.8

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.0

1.1

1.2

1.5

2.2

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.4

1.7

1.9

2.2

3.0

ns

0.3

0.4

0.7

ns

Minimum Period

2.8

3.4

3.8

4.4

6.0

ns

f_HMAX

Maximum Frequency

357

294

263

227

167

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

1.0

1.1

1.3

1.2

1.3

1.5

1.3

1.5

1.7

1.6

1.7

2.0

2.2

2.4

2.8

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.4

1.7

1.9

2.2

3.0

ns

t_RPWL

t_RCKSW

0.8

1.0

0.9

1.1

1.0

1.3

1.2

1.5

1.7

2.1

Note: *All –3 speed grades have been discontinued.

2-28

v5.3

SX-A Family FPGAs

Table 2-23 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.2

1.4

1.6

1.8

2.8

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.0

1.1

1.3

1.5

2.2

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.4

1.7

1.9

2.2

3.0

ns

0.3

0.4

0.6

ns

Minimum Period

2.8

3.4

3.8

4.4

6.0

ns

f_HMAX

Maximum Frequency

357

294

263

227

167

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

1.0

1.1

1.3

1.2

1.3

1.5

1.3

1.5

1.4

1.5

1.7

1.5

1.7

2.0

2.1

2.4

2.3

2.4

2.7

2.8

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.4

1.7

1.9

2.2

3.0

ns

t_RPWL

t_RCKSW

0.8

1.0

0.9

1.1

1.0

1.3

1.2

1.5

1.7

2.1

Note: *All –3 speed grades have been discontinued.

v5.3

2-29

SX-A Family FPGAs

Table 2-24 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI=4.75 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.2

1.4

1.6

1.8

2.8

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.0

1.1

1.2

1.5

2.2

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.4

1.7

1.9

2.2

3.0

ns

0.3

0.4

0.7

ns

Minimum Period

2.8

3.4

3.8

4.4

6.0

ns

f_HMAX

Maximum Frequency

357

294

263

227

167

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

1.0

1.1

1.3

1.2

1.3

1.5

1.3

1.5

1.7

1.6

1.7

2.0

2.2

2.4

2.8

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.4

1.7

1.9

2.2

3.0

ns

t_RPWL

t_RCKSW

0.8

1.0

0.9

1.1

1.0

1.3

1.2

1.5

1.7

2.1

Note: *All –3 speed grades have been discontinued.

2-30

v5.3

SX-A Family FPGAs

Table 2-25 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.25 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

2.5 V LVCMOS Output Module Timing ^{2, 3}

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

3.4

2.6

3.9

3.0

4.5

3.3

5.2

3.9

7.3

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

11.6

2.4

13.4

2.8

15.2

3.2

17.9

3.7

25.0

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

11.8

3.4

13.7

3.9

15.5

4.5

18.2

5.2

25.5

7.3

Enable-to-Pad, L to Z

2.1

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

2.6

3.0

3.3

3.9

5.5

4

d_TLH

Delta Low to High

0.031

0.017

0.057

0.037

0.017

0.06

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

4

d_THL

Delta High to Low

4

d_THLS

Delta High to Low—low slew

Note:

1. All –3 speed grades have been discontinued.

2. Delays based on 35 pF loading.

3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.

4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

v5.3

2-31

SX-A Family FPGAs

Table 2-26 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter

Description

3.3 V PCI Output Module Timing²

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

2.0

2.2

2.3

2.5

2.6

2.8

3.1

3.3

4.3

4.6

3.1

4.3

5.3

4.6

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.4

1.7

1.9

2.2

2.0

2.3

2.6

3.1

2.5

2.8

3.2

3.8

2.2

2.5

2.8

3.3

3

d_TLH

0.025

0.015

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

3

d_THL

Delta High to Low

3.3 V LVTTL Output Module Timing⁴

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

2.8

2.7

3.2

3.1

3.6

3.5

4.3

4.1

6.0

5.7

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

9.5

10.9

2.6

12.4

2.9

14.6

3.4

20.4

4.8

2.2

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

15.8

2.8

18.9

3.2

21.3

3.6

25.4

4.3

34.9

6.0

Enable-to-Pad, L to Z

2.9

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

2.7

3.1

3.5

4.1

5.7

3

d_TLH

Delta Low to High

0.025

0.015

0.053

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

3

d_THL

Delta High to Low

3

d_THLS

Delta High to Low—low slew

Notes:

1. All –3 speed grades have been discontinued.

2. Delays based on 10 pF loading and 25 Ω resistance.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

4. Delays based on 35 pF loading.

2-32

v5.3

SX-A Family FPGAs

Table 2-27 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

5 V PCI Output Module Timing²

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

2.2

2.8

2.5

3.2

2.8

3.6

3.3

4.2

4.6

5.9

2.8

4.6

6.4

5.9

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.3

1.5

1.7

2.0

2.2

2.5

2.8

3.3

3.0

3.5

3.9

4.6

2.8

3.2

3.6

4.2

3

d_TLH

0.016

0.026

0.016

0.03

0.02

0.032

0.022

0.04

0.032 ns/pF

0.052 ns/pF

3

d_THL

Delta High to Low

5 V TTL Output Module Timing⁴

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

2.2

2.8

2.5

3.2

2.8

3.6

3.3

4.2

4.6

5.9

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

6.7

7.7

8.7

10.2

3.2

14.3

4.5

2.1

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

7.4

8.4

9.5

11.0

2.9

15.4

4.1

1.9

2.2

2.5

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

2.5

2.9

3.3

3.9

5.4

3

d_TLH

Delta Low to High

0.014

0.023

0.043

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

3

d_THL

Delta High to Low

3

d_THLS

Delta High to Low—low slew

Notes:

1. All –3 speed grades have been discontinued.

2. Delays based on 50 pF loading.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

4. Delays based on 35 pF loading.

v5.3

2-33

SX-A Family FPGAs

Table 2-28 • A54SX32A Timing Characteristics

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–3 Speed¹

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

–2 Speed

–1 Speed

Std. Speed

–F Speed

Parameter

C-Cell Propagation Delays²

t_PDInternal Array Module

Predicted Routing Delays³

Description

0.8

0.1

0.9

0.1

1.1

0.1

1.2

0.1

1.7

0.1

ns

t_DC

FO

= 1 Routing Delay, Direct

Connect

t_FC

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.6

0.8

1.4

2.0

0.3

0.4

0.5

0.7

0.9

1.5

2.2

0.4

0.5

0.6

0.8

1.0

1.8

2.6

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.6

0.5

0.6

0.7

0.6

0.7

0.8

0.6

0.7

0.9

0.8

0.9

1.3

1.0

1.2

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Clock Pulse Width

t_PRESET

t_SUD

0.6

0.0

1.2

0.3

1.4

0.7

0.0

1.4

0.4

0.3

1.6

0.8

0.0

1.5

0.4

0.3

1.8

0.9

0.0

1.8

0.5

0.4

2.1

1.2

0.0

2.5

0.7

0.6

2.9

t_HD

t_WASYN

t_RECASYN

t_HASYN

t_MPW

Input Module Propagation Delays

t_INYHInput Data Pad to Y High 2.5 V

0.6

1.2

0.7

1.3

0.8

1.5

0.9

1.8

1.2

2.5

ns

LVCMOS

t_INYL

Input Data Pad to Y Low 2.5 V

LVCMOS

t_INYH

t_INYL

t_INYH

Input Data Pad to Y High 3.3 V PCI

Input Data Pad to Y Low 3.3 V PCI

0.5

0.6

0.8

0.6

0.7

0.9

0.6

0.8

1.0

0.7

0.9

1.2

1.0

1.3

1.6

ns

Input Data Pad to Y High 3.3 V

LVTTL

t_INYL

Input Data Pad to Y Low 3.3 V LVTTL

1.4

1.6

1.8

2.2

3.0

ns

Notes:

1. All –3 speed grades have been discontinued.

2. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2-34

v5.3

SX-A Family FPGAs

Std. Speed –F Speed

Table 2-28 • A54SX32A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–3 Speed¹

–2 Speed

–1 Speed

Parameter

t_INYH

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Data Pad to Y High 5 V PCI

Input Data Pad to Y Low 5 V PCI

Input Data Pad to Y High 5 V TTL

Input Data Pad to Y Low 5 V TTL

0.7

0.9

1.4

0.8

1.1

1.6

0.9

1.2

1.8

1.0

1.4

2.1

1.4

1.9

2.9

ns

t_INYL

t_INYH

t_INYL

Input Module Predicted Routing Delays³

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.6

0.8

1.4

2

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1

0.6

0.8

1.1

1.4

2.5

3.6

ns

t_IRD2

t_IRD3

t_IRD4

t_IRD8

1.8

2.6

t_IRD12

Notes:

1. All –3 speed grades have been discontinued.

2. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5.3

2-35

SX-A Family FPGAs

Table 2-29 • A54SX32A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.25 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.7

2.0

2.2

2.6

4.0

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.7

2.0

2.2

2.6

4.0

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.4

1.6

1.8

2.1

2.9

ns

0.6

0.7

0.8

1.3

ns

Minimum Period

2.8

3.2

3.6

4.2

5.8

ns

f_HMAX

Maximum Frequency

357

313

278

238

172

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

2.2

2.1

2.4

2.2

2.5

2.4

2.5

2.4

2.7

2.5

2.9

2.7

2.9

2.7

3.1

2.8

3.2

3.1

3.4

3.2

3.6

3.3

3.8

3.6

4.7

4.4

5.1

4.6

5.3

5.0

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.4

1.6

1.8

2.1

2.9

ns

t_RPWL

t_RCKSW

1.0

0.9

1.1

1.0

1.3

1.2

1.5

1.4

2.1

1.9

Note: *All –3 speed grades have been discontinued.

2-36

v5.3

SX-A Family FPGAs

Table 2-30 • A54SX32A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.7

2.0

2.2

2.6

4.0

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.7

2.0

2.2

2.6

4.0

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.4

1.6

1.8

2.1

2.9

ns

0.6

0.7

0.8

1.3

ns

Minimum Period

2.8

3.2

3.6

4.2

5.8

ns

f_HMAX

Maximum Frequency

357

313

278

238

172

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

2.2

2.1

2.3

2.2

2.4

2.5

2.4

2.7

2.5

2.8

2.7

3.1

2.9

3.2

3.1

3.3

3.2

3.6

3.4

3.7

4.6

4.5

5

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

4.7

5.2

5.1

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.4

1.6

1.8

2.1

2.9

ns

t_RPWL

t_RCKSW

1.0

0.9

1.1

1.0

1.3

1.2

1.5

1.4

2.1

1.9

Note: *All –3 speed grades have been discontinued.

v5.3

2-37

SX-A Family FPGAs

Table 2-31 • A54SX32A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.7

1.9

2.2

2.6

4.0

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.7

2.0

2.2

2.6

4.0

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.4

1.6

1.8

2.1

2.9

ns

0.6

0.7

0.8

1.3

ns

Minimum Period

2.8

3.2

3.6

4.2

5.8

ns

f_HMAX

Maximum Frequency

357

313

278

238

172

MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

2.2

2.1

2.4

2.2

2.5

2.4

2.5

2.7

2.6

2.8

3.1

2.9

3.2

3.1

3.3

3.6

3.4

3.8

3.7

4.7

4.5

5.1

4.7

5.3

5.2

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.4

1.6

1.8

2.1

2.9

ns

t_RPWL

t_RCKSW

1.0

1.1

1.3

1.5

2.1

Note: *All –3 speed grades have been discontinued.

2-38

v5.3

SX-A Family FPGAs

Table 2-32 • A54SX32A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.3 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

2.5 V LVCMOS Output Module Timing ^2,3

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

3.3

2.5

3.8

2.9

4.2

3.2

5.0

3.8

7.0

5.3

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

11.1

2.4

12.8

2.8

14.5

3.2

17.0

3.7

23.8

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

11.8

3.3

13.7

3.8

15.5

4.2

18.2

5.0

25.5

7.0

Enable-to-Pad, L to Z

2.1

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

2.5

2.9

3.2

3.8

5.3

4

d_TLH

Delta Low to High

0.031

0.017

0.057

0.037

0.017

0.06

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

4

d_THL

Delta High to Low

4

d_THLS

Delta High to Low—low slew

Note:

1. All –3 speed grades have been discontinued.

2. Delays based on 35 pF loading.

3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.

4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

v5.3

2-39

SX-A Family FPGAs

Table 2-33 • A54SX32A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter

Description

3.3 V PCI Output Module Timing²

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

1.9

2.0

2.2

2.3

2.4

2.6

2.9

3.1

4.0

4.3

3.1

4.0

5.3

4.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.4

1.7

1.9

2.2

1.9

2.2

2.4

2.9

2.5

2.8

3.2

3.8

2.0

2.3

2.6

3.1

3

d_TLH

0.025

0.015

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

3

d_THL

Delta High to Low

3.3 V LVTTL Output Module Timing⁴

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

2.6

3.0

3.4

3.3

4.0

3.9

5.6

5.5

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

9.0

10.4

2.6

11.8

2.9

13.8

3.4

19.3

4.8

2.2

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

15.8

2.6

18.9

3.0

21.3

3.4

25.4

4.0

34.9

5.6

Enable-to-Pad, L to Z

2.9

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

2.6

3.0

3.3

3.9

5.5

3

d_TLH

Delta Low to High

0.025

0.015

0.053

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

3

d_THL

Delta High to Low

3

d_THLS

Delta High to Low—low slew

Notes:

1. All –3 speed grades have been discontinued.

2. Delays based on 10 pF loading and 25 Ω resistance.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

4. Delays based on 35 pF loading.

2-40

v5.3

SX-A Family FPGAs

Table 2-34 • A54SX32A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

5 V PCI Output Module Timing²

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

2.1

2.8

2.4

3.2

2.8

3.6

3.2

4.2

4.5

5.9

2.8

4.5

6.4

5.9

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.3

1.5

1.7

2.0

2.1

2.4

2.8

3.2

3.0

3.5

3.9

4.6

2.8

3.2

3.6

4.2

3

d_TLH

0.016

0.026

0.016

0.03

0.02

0.032

0.022

0.04

0.032 ns/pF

0.052 ns/pF

3

d_THL

Delta High to Low

5 V TTL Output Module Timing⁴

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

1.9

2.5

2.2

2.9

2.5

3.3

2.9

3.9

4.1

5.4

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

6.6

7.6

8.6

10.1

3.2

14.2

4.5

2.1

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

7.4

8.4

9.5

11.0

2.9

15.4

4.1

1.9

2.2

2.5

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

2.5

2.9

3.3

3.9

5.4

3

d_TLH

Delta Low to High

0.014

0.023

0.043

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

3

d_THL

Delta High to Low

3

d_THLS

Delta High to Low—low slew

Notes:

1. All –3 speed grades have been discontinued.

2. Delays based on 50 pF loading.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

4. Delays based on 35 pF loading.

v5.3

2-41

SX-A Family FPGAs

Table 2-35 • A54SX72A Timing Characteristics

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–3 Speed¹

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

–2 Speed

–1 Speed

Std. Speed

–F Speed

Parameter

C-Cell Propagation Delays²

t_PDInternal Array Module

Predicted Routing Delays³

Description

1.0

0.1

1.1

0.1

1.3

0.1

1.5

0.1

2.0

0.1

ns

t_DC

FO

= 1 Routing Delay, Direct

Connect

t_FC

FO = 1 Routing Delay, Fast Connect

FO = 1 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.7

0.9

1.5

2.2

0.3

0.4

0.6

0.8

1

0.4

0.5

0.7

0.9

1.1

2.1

3

0.6

0.7

1

ns

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

t_RD12

FO = 2 Routing Delay

FO = 3 Routing Delay

1.3

1.5

2.9

4.2

FO = 4 Routing Delay

FO = 8 Routing Delay

1.7

2.5

FO = 12 Routing Delay

R-Cell Timing

t_RCO

Sequential Clock-to-Q

0.7

0.6

0.7

0.8

0.7

0.8

0.9

0.7

0.8

1.1

0.9

1.0

1.5

1.2

1.4

ns

t_CLR

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Data Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Hold Time

Clock Minimum Pulse Width

t_PRESET

t_SUD

0.7

0.0

1.3

0.3

1.5

0.8

0.0

1.5

0.4

0.3

1.7

0.9

0.0

1.7

0.4

0.3

2.0

1.0

0.0

2.0

0.5

0.4

2.3

1.4

0.0

2.8

0.7

0.6

3.2

t_HD

t_WASYN

t_RECASYN

t_HASYN

t_MPW

Input Module Propagation Delays

t_INYHInput Data Pad to Y High 2.5 V

0.6

0.8

0.7

1.0

0.8

1.1

0.9

1.3

1.7

ns

LVCMOS

t_INYL

Input Data Pad to Y Low 2.5 V

LVCMOS

t_INYH

t_INYL

t_INYH

Input Data Pad to Y High 3.3 V PCI

Input Data Pad to Y Low 3.3 V PCI

0.6

0.7

0.8

0.7

0.9

0.8

0.9

1.0

1.2

1.4

ns

Input Data Pad to Y High 3.3 V

LVTTL

t_INYL

Input Data Pad to Y Low 3.3 V LVTTL

1.0

1.2

1.3

1.5

2.1

ns

Notes:

1. All –3 speed grades have been discontinued.

2. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

2-42

v5.3

SX-A Family FPGAs

Std. Speed –F Speed

Table 2-35 • A54SX72A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions, V_CCA= 2.25 V V_CCI= 3.0 V, T_J= 70°C)

,

–3 Speed¹

–2 Speed

–1 Speed

Parameter

t_INYH

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Data Pad to Y High 5 V PCI

Input Data Pad to Y Low 5 V PCI

Input Data Pad to Y High 5 V TTL

Input Data Pad to Y Low 5 V TTL

0.5

0.8

0.7

0.9

0.6

0.9

0.8

1.1

0.7

1.0

0.9

1.2

0.8

1.2

1.0

1.4

1.1

1.6

1.4

1.9

ns

t_INYL

t_INYH

t_INYL

Input Module Predicted Routing Delays³

t_IRD1

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

FO = 12 Routing Delay

0.3

0.4

0.5

0.7

1.2

1.7

0.3

0.5

0.7

0.9

1.5

2.2

0.4

0.6

0.8

1

0.5

0.7

0.9

1.1

2.1

3

0.7

1

ns

t_IRD2

t_IRD3

1.3

1.5

2.9

4.2

t_IRD4

t_IRD8

1.7

2.5

t_IRD12

Notes:

1. All –3 speed grades have been discontinued.

2. For dual-module macros, use t_PD+ t_RD1+ t_PDn, t_RCO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

v5.3

2-43

SX-A Family FPGAs

Table 2-36 • A54SX72A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.25 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Std. Speed

–F Speed

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.6

1.9

2.1

2.5

3.8

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.6

1.9

2.1

2.5

3.8

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.5

1.7

2.0

2.3

3.2

ns

1.4

1.6

1.8

2.1

3.3

Minimum Period

3.0

3.4

4.0

4.6

6.4

f_HMAX

Maximum Frequency

333

294

250

217

156 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

2.3

2.8

2.4

2.9

2.6

3.1

2.6

3.2

2.8

3.3

3.0

3.6

2.9

3.7

3.2

3.8

3.4

4.0

3.4

4.3

3.7

4.5

4.0

4.7

4.8

6.0

5.2

6.2

5.6

6.6

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.5

1.7

2.0

2.3

3.2

ns

t_RPWL

t_RCKSW

1.9

1.8

2.2

2.1

2.5

2.4

3.0

2.8

4.1

3.9

Quadrant Array Clock Networks

t_QCKH

t_QCHKL

t_QCKH

t_QCHKL

Input Low to High (Light Load)

(Pad to R-cell Input)

2.6

2.8

3.0

3.2

3.4

3.3

3.6

4.0

3.9

4.3

4.2

5.6

5.5

6.0

5.9

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Note: *All –3 speed grades have been discontinued.

2-44

v5.3

SX-A Family FPGAs

Std. Speed –F Speed

Table 2-36 • A54SX72A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.25 V, T_J= 70°C)

–3 Speed*

–2 Speed

–1 Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_QCKH

Input Low to High (100% Load)

(Pad to R-cell Input)

3.0

3.4

3.9

4.6

6.4

ns

t_QCHKL

Input High to Low (100% Load)

(Pad to R-cell Input)

2.9

3.4

3.8

4.5

6.3

ns

t_QPWH

t_QPWL

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.5

1.7

2.0

2.3

3.2

ns

t_QCKSW

0.2

0.4

0.3

0.5

0.3

0.5

0.3

0.6

0.5

0.9

Note: *All –3 speed grades have been discontinued.

v5.3

2-45

SX-A Family FPGAs

Table 2-37 • A54SX72A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Std. Speed

–F Speed

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.6

1.9

2.1

2.5

3.8

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.7

1.9

2.1

2.5

3.8

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.5

1.7

2.0

2.3

3.2

ns

1.4

1.6

1.8

2.1

3.3

Minimum Period

3.0

3.4

4.0

4.6

6.4

f_HMAX

Maximum Frequency

333

294

250

217

156 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

2.2

2.8

2.4

2.9

2.6

3.1

2.6

3.3

2.8

3.4

3.0

3.6

2.9

3.7

3.2

3.8

3.4

4.1

3.4

4.3

3.7

4.5

4.0

4.8

6.0

5.2

6.2

5.6

6.7

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.5

1.7

2.0

2.3

3.2

ns

t_RPWL

t_RCKSW

1.9

2.2

2.1

2.5

2.4

3

4.1

3.9

2.8

Quadrant Array Clock Networks

t_QCKH

t_QCHKL

t_QCKH

t_QCHKL

Input Low to High (Light Load)

(Pad to R-cell Input)

1.3

1.5

1.7

1.8

1.7

1.9

2

1.9

2

2.7

2.8

3.1

3.2

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

2.2

2.3

Input High to Low (50% Load)

(Pad to R-cell Input)

Note: *All –3 speed grades have been discontinued.

2-46

v5.3

SX-A Family FPGAs

Std. Speed –F Speed

Table 2-37 • A54SX72A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–3 Speed*

–2 Speed

–1 Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_QCKH

Input Low to High (100% Load)

(Pad to R-cell Input)

1.7

1.9

2.2

2.5

3.5

ns

t_QCHKL

Input High to Low (100% Load)

(Pad to R-cell Input)

1.7

2

2.2

2.6

3.6

ns

t_QPWH

t_QPWL

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.5

1.7

2.0

2.3

3.2

ns

t_QCKSW

0.2

0.4

0.3

0.5

0.3

0.5

0.3

0.6

0.5

0.9

Note: *All –3 speed grades have been discontinued.

v5.3

2-47

SX-A Family FPGAs

Table 2-38 • A54SX72A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–3 Speed* –2 Speed –1 Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Dedicated (Hardwired) Array Clock Networks

Std. Speed

–F Speed

Parameter

Description

t_HCKH

Input Low to High

(Pad to R-cell Input)

1.6

1.8

2.1

2.4

3.8

ns

t_HCKL

Input High to Low

(Pad to R-cell Input)

1.6

1.9

2.1

2.5

3.8

ns

t_HPWH

t_HPWL

t_HCKSW

t_HP

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

1.5

1.7

2.0

2.3

3.2

ns

1.4

1.6

1.8

2.1

3.3

Minimum Period

3.0

3.4

4.0

4.6

6.4

f_HMAX

Maximum Frequency

333

294

250

217

156 MHz

Routed Array Clock Networks

t_RCKH

t_RCKL

t_RCKH

t_RCKL

t_RCKH

t_RCKL

Input Low to High (Light Load)

(Pad to R-cell Input)

2.3

2.8

2.5

3.0

2.6

3.2

2.6

3.2

2.9

3.4

3.0

3.6

3.0

3.6

3.2

3.9

3.4

4.1

3.5

4.3

3.8

4.6

3.9

4.8

4.9

6.0

5.3

6.4

5.5

6.8

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Input Low to High (100% Load)

(Pad to R-cell Input)

Input High to Low (100% Load)

(Pad to R-cell Input)

t_RPWH

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.5

1.7

2.0

2.3

3.2

ns

t_RPWL

t_RCKSW

1.9

2.2

2.5

3.0

4.1

Quadrant Array Clock Networks

t_QCKH

t_QCHKL

t_QCKH

t_QCHKL

Input Low to High (Light Load)

(Pad to R-cell Input)

1.2

1.3

1.4

1.6

1.7

1.6

1.8

1.9

1.8

1.9

2.1

2.2

2.6

2.7

3.0

3.1

ns

Input High to Low (Light Load)

(Pad to R-cell Input)

Input Low to High (50% Load)

(Pad to R-cell Input)

Input High to Low (50% Load)

(Pad to R-cell Input)

Note: *All –3 speed grades have been discontinued.

2-48

v5.3

SX-A Family FPGAs

Std. Speed –F Speed

Table 2-38 • A54SX72A Timing Characteristics (Continued)

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–3 Speed*

–2 Speed

–1 Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_QCKH

Input Low to High (100% Load)

(Pad to R-cell Input)

1.6

1.8

2.1

2.4

3.4

ns

t_QCHKL

Input High to Low (100% Load)

(Pad to R-cell Input)

1.6

1.9

2.1

2.5

3.5

ns

t_QPWH

t_QPWL

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew (Light Load)

Maximum Skew (50% Load)

Maximum Skew (100% Load)

1.5

1.7

2.0

2.3

3.2

ns

t_QCKSW

0.2

0.4

0.3

0.5

0.3

0.5

0.3

0.6

0.5

0.9

Note: *All –3 speed grades have been discontinued.

v5.3

2-49

SX-A Family FPGAs

Table 2-39 • A54SX72A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 2.3 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter

Description

2.5 V LVCMOS Output Module Timing^{2, 3}

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

3.9

3.1

4.5

3.6

5.1

4.1

6.0

4.8

8.4

6.7

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

12.7

2.4

14.6

2.8

16.5

3.2

19.4

3.7

27.2

5.2

Data-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

11.8

3.9

13.7

4.5

15.5

5.1

18.2

6.0

25.5

8.4

Enable-to-Pad, L to Z

2.1

2.5

2.8

3.3

4.7

Enable-to-Pad, H to Z

3.1

3.6

4.1

4.8

6.7

4

d_TLH

Delta Low to High

0.031

0.017

0.057

0.037

0.017

0.06

0.043

0.023

0.071

0.051

0.023

0.086

0.071 ns/pF

0.037 ns/pF

0.117 ns/pF

4

d_THL

Delta High to Low

4

d_THLS

Delta High to Low—low slew

Note:

1. All –3 speed grades have been discontinued.

2. Delays based on 35 pF loading.

3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.

4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

2-50

v5.3

SX-A Family FPGAs

Table 2-40 • A54SX72A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 3.0 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

3.3 V PCI Output Module Timing²

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

2.3

2.5

2.7

2.9

3.0

3.2

3.6

3.8

5.0

5.3

3.1

5.0

5.3

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.4

1.7

1.9

2.2

2.3

2.7

3.0

3.6

2.5

2.8

3.2

3.8

2.5

2.9

3.2

3.8

3

d_TLH

0.025

0.015

0.03

0.015

0.03

0.015

0.04

0.015

0.045 ns/pF

0.025 ns/pF

3

d_THL

Delta High to Low

3.3 V LVTTL Output Module Timing⁴

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

3.2

3.7

4.2

5.0

4.9

6.9

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

10.3

2.2

11.9

2.6

13.5

2.9

15.8

3.4

22.2

4.8

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

15.8

3.2

18.9

3.7

21.3

4.2

25.4

5.0

34.9

6.9

Enable-to-Pad, L to Z

2.9

3.3

3.7

4.4

6.2

Enable-to-Pad, H to Z

3.2

3.7

4.2

4.9

6.9

3

d_TLH

Delta Low to High

0.025

0.015

0.053

0.03

0.015

0.053

0.03

0.015

0.067

0.04

0.015

0.073

0.045 ns/pF

0.025 ns/pF

0.107 ns/pF

3

d_THL

Delta High to Low

3

d_THLS

Delta High to Low—low slew

Notes:

1. All –3 speed grades have been discontinued.

2. Delays based on 10 pF loading and 25 Ω resistance.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

4. Delays based on 35 pF loading.

v5.3

2-51

SX-A Family FPGAs

Table 2-41 • A54SX72A Timing Characteristics

(Worst-Case Commercial Conditions V_CCA= 2.25 V, V_CCI= 4.75 V, T_J= 70°C)

–3 Speed¹

–2 Speed –1 Speed Std. Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter

Description

5 V PCI Output Module Timing²

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Enable-to-Pad, Z to L

Enable-to-Pad, Z to H

Enable-to-Pad, L to Z

Enable-to-Pad, H to Z

Delta Low to High

2.7

3.4

3.1

3.9

3.5

4.4

4.1

5.1

5.7

7.2

2.8

5.7

6.4

7.2

ns

t_DHL

t_ENZL

t_ENZH

t_ENLZ

t_ENHZ

1.3

1.5

1.7

2.0

2.7

3.1

3.5

4.1

3.0

3.5

3.9

4.6

3.4

3.9

4.4

5.1

3

d_TLH

0.016

0.026

0.016

0.03

0.02

0.032

0.022

0.04

0.032 ns/pF

0.052 ns/pF

3

d_THL

Delta High to Low

5 V TTL Output Module Timing⁴

t_DLH

Data-to-Pad Low to High

Data-to-Pad High to Low

Data-to-Pad High to Low—low slew

Enable-to-Pad, Z to L

2.4

3.1

2.8

3.5

3.1

4.0

3.7

4.7

5.1

6.6

ns

t_DHL

t_DHLS

t_ENZL

t_ENZLS

t_ENZH

t_ENLZ

t_ENHZ

7.4

8.5

9.7

11.4

3.2

15.9

4.5

2.1

2.4

2.7

Enable-to-Pad, Z to L—low slew

Enable-to-Pad, Z to H

7.4

8.4

9.5

11.0

3.7

15.4

5.1

2.4

2.8

3.1

Enable-to-Pad, L to Z

3.6

4.2

4.7

5.6

7.8

Enable-to-Pad, H to Z

3.1

3.5

4.0

4.7

6.6

3

d_TLH

Delta Low to High

0.014

0.023

0.043

0.017

0.029

0.046

0.017

0.031

0.057

0.023

0.037

0.066

0.031 ns/pF

0.051 ns/pF

0.089 ns/pF

3

d_THL

Delta High to Low

3

d_THLS

Delta High to Low—low slew

Notes:

1. All –3 speed grades have been discontinued.

2. Delays based on 50 pF loading.

3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the V_CCIvalue into the following equation:

Slew Rate [V/ns] = (0.1*V_CCI– 0.9*V_CCI)/ (C_load* d_T[LH|HL|HLS]

where C_loadis the load capacitance driven by the I/O in pF

)

d_T[LH|HL|HLS]is the worst case delta value from the datasheet in ns/pF.

4. Delays based on 35 pF loading.

2-52

v5.3

SX-A Family FPGAs

Package Pin Assignments

208-Pin PQFP

208

1

208-Pin

PQFP

Figure 3-1 • 208-Pin PQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v5.3

3-1

SX-A Family FPGAs

208-Pin PQFP

A54SX08A A54SX16A A54SX32A A54SX72A

208-Pin PQFP

Number Function Function Function Function

A54SX08A A54SX16A A54SX32A A54SX72A

Number Function Function Function Function

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

NC

I/O

V_CCI

V_CCA

I/O

GND

I/O

V_CCI

I/O

2

3

I/O

4

NC

I/O

NC

V_CCI

V_CCA

I/O

5

I/O

6

NC

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

TMS

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

V_CCA

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

NC

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

GND

V_CCA

GND

I/O

NC

I/O

TRST, I/O

NC

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

NC

I/O

NC

I/O

NC

3-2

v5.3

SX-A Family FPGAs

208-Pin PQFP

A54SX08A A54SX16A A54SX32A A54SX72A

Number Function Function Function Function

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

I/O

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

NC

I/O

NC

I/O

NC

I/O

QCLKA

I/O

NC

I/O

PRB, I/O

GND

V_CCA

GND

NC

PRB, I/O

GND

V_CCA

GND

NC

PRB, I/O

GND

V_CCA

GND

NC

PRB,I/O

GND

V_CCA

GND

NC

I/O

V_CCA

V_CCI

NC

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

GND

V_CCA

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

HCLK

V_CCI

QCLKB

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

V_CCA

GND

NC

I/O

GND

V_CCA

GND

NC

I/O

GND

V_CCA

GND

NC

I/O

GND

V_CCA

GND

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

NC

I/O

GND

I/O

v5.3

3-3

SX-A Family FPGAs

208-Pin PQFP

A54SX08A A54SX16A A54SX32A A54SX72A

208-Pin PQFP

Number Function Function Function Function

A54SX08A A54SX16A A54SX32A A54SX72A

Number Function Function Function Function

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

NC

I/O

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

NC

I/O

NC

I/O

QCLKD

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

CLKA

CLKB

NC

CLKA

CLKB

NC

CLKA

CLKB

NC

CLKA

CLKB

NC

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

GND

V_CCA

GND

PRA, I/O

I/O

GND

V_CCA

GND

PRA, I/O

I/O

GND

V_CCA

GND

PRA, I/O

I/O

GND

V_CCA

GND

PRA, I/O

V_CCI

I/O

NC

I/O

NC

GND

I/O

QCLKC

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

NC

I/O

NC

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

NC

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

TCK, I/O

I/O

3-4

v5.3

SX-A Family FPGAs

100-Pin TQFP

100

1

100-Pin

TQFP

Figure 3-2 • 100-Pin TQFP

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v5.3

3-5

SX-A Family FPGAs

100-TQFP

A54SX08A A54SX16A

100-TQFP

A54SX32A

Function

A54SX08A

A54SX16A

Function

A54SX32A

Function

Pin Number

Function

GND

TDI, I/O

I/O

Function

GND

TDI, I/O

I/O

Pin Number

Function

GND

NC

1

GND

TDI, I/O

I/O

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

GND

NC

GND

NC

2

3

I/O

4

I/O

HCLK

I/O

HCLK

I/O

HCLK

I/O

5

I/O

6

I/O

7

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

8

I/O

9

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

V_CCI

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

PRB, I/O

V_CCA

PRB, I/O

V_CCA

PRB, I/O

V_CCA

3-6

v5.3

SX-A Family FPGAs

100-TQFP

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

Pin Number

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

CLKA

CLKB

NC

CLKA

CLKB

NC

CLKA

CLKB

NC

V_CCA

GND

PRA, I/O

I/O

V_CCA

GND

PRA, I/O

I/O

V_CCA

GND

PRA, I/O

I/O

TCK, I/O

v5.3

3-7

SX-A Family FPGAs

144-Pin TQFP

144

1

144-Pin

TQFP

Figure 3-3 • 144-Pin TQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-8

v5.3

SX-A Family FPGAs

144-Pin TQFP

A54SX08A A54SX16A

A54SX08A

A54SX16A

Function

A54SX32A

Function

A54SX32A

Function

Pin Number

Function

GND

TDI, I/O

I/O

Pin Number

38

Function

1

GND

TDI, I/O

I/O

GND

TDI, I/O

I/O

2

39

I/O

3

40

I/O

4

I/O

41

I/O

5

I/O

42

I/O

6

I/O

43

I/O

7

I/O

44

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

8

I/O

45

9

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

TMS

V_CCI

GND

I/O

46

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

47

I/O

48

I/O

49

I/O

50

I/O

51

I/O

52

I/O

53

I/O

54

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

55

NC

56

V_CCA

GND

NC

V_CCA

GND

NC

V_CCA

GND

NC

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

57

58

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

59

I/O

60

HCLK

I/O

HCLK

I/O

HCLK

I/O

61

I/O

62

I/O

63

I/O

64

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

GND

V_CCI

V_CCA

I/O

65

I/O

66

I/O

67

I/O

68

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

69

I/O

70

I/O

71

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

72

GND

I/O

GND

I/O

GND

I/O

73

GND

I/O

GND

I/O

GND

I/O

74

v5.3

3-9

SX-A Family FPGAs

144-Pin TQFP

A54SX08A A54SX16A

144-Pin TQFP

A54SX32A

Function

A54SX08A

A54SX16A

Function

A54SX32A

Function

Pin Number

75

Function

Pin Number

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Function

I/O

76

I/O

77

I/O

78

I/O

79

V_CCA

V_CCI

GND

I/O

V_CCA

V_CCI

GND

I/O

V_CCA

V_CCI

GND

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

80

81

I/O

82

I/O

83

I/O

84

I/O

85

I/O

86

I/O

87

I/O

88

I/O

89

V_CCA

NC

V_CCA

NC

V_CCA

NC

I/O

CLKA

CLKB

NC

CLKA

CLKB

NC

CLKA

CLKB

NC

90

91

I/O

92

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O

GND

V_CCA

I/O

93

I/O

94

I/O

95

I/O

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

I/O

96

I/O

97

I/O

98

V_CCA

GND

I/O

V_CCA

GND

I/O

V_CCA

GND

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

TCK, I/O

GND

I/O

GND

I/O

GND

I/O

3-10

v5.3

SX-A Family FPGAs

176-Pin TQFP

176

1

176-Pin

TQFP

Figure 3-4 • 176-Pin TQFP (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v5.3

3-11

SX-A Family FPGAs

176-Pin TQFP

Number

A54SX32A

Function

Number

A54SX32A

Function

A54SX32A

Function

GND

TDI, I/O

I/O

Number

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

Number

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

1

I/O

73

I/O

V_CCA

GND

I/O

2

74

3

I/O

75

I/O

4

I/O

76

I/O

5

I/O

77

I/O

6

I/O

78

I/O

7

I/O

79

I/O

8

I/O

GND

I/O

80

I/O

9

I/O

81

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

TMS

V_CCI

I/O

82

V_CCI

I/O

83

I/O

84

I/O

85

I/O

86

I/O

V_CCA

GND

V_CCI

I/O

87

TDO, I/O

I/O

V_CCI

I/O

88

I/O

89

GND

I/O

90

I/O

91

I/O

92

I/O

GND

V_CCA

GND

I/O

93

I/O

94

I/O

95

I/O

96

I/O

TRST, I/O

I/O

97

I/O

GND

I/O

98

V_CCA

V_CCI

I/O

99

I/O

PRB, I/O

GND

V_CCA

NC

I/O

100

101

102

103

104

105

106

107

108

I/O

V_CCI

V_CCA

I/O

V_CCI

I/O

HCLK

I/O

GND

I/O

3-12

v5.3

SX-A Family FPGAs

176-Pin TQFP

A54SX32A

Function

Number

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

I/O

CLKA

CLKB

NC

GND

V_CCA

PRA, I/O

I/O

V_CCI

I/O

TCK, I/O

v5.3

3-13

SX-A Family FPGAs

329-Pin PBGA

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

Figure 3-5 • 329-Pin PBGA (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-14

v5.3

SX-A Family FPGAs

329-Pin PBGA

Number

A54SX32A

Function

A54SX32A

Function

A54SX32A

Function

A54SX32A

Function

Number

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AB1

Number

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

B1

Number

B20

B21

B22

B23

C1

A1

GND

V_CCI

NC

I/O

A2

A3

I/O

GND

V_CCI

NC

A4

I/O

V_CCI

I/O

A5

I/O

A6

I/O

TDO, I/O

V_CCI

I/O

C2

TDI, I/O

GND

I/O

A7

V_CCI

NC

I/O

C3

A8

I/O

C4

A9

V_CCI

I/O

C5

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

I/O

NC

I/O

C6

I/O

AB2

GND

I/O

C7

I/O

AB3

I/O

C8

I/O

CLKB

I/O

AB4

I/O

C9

I/O

AB5

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

I/O

AB6

I/O

AB7

I/O

NC

V_CCI

GND

V_CCI

GND

I/O

AB8

I/O

AB9

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

I/O

PRB, I/O

I/O

B2

I/O

NC

V_CCI

GND

V_CCI

I/O

B3

I/O

HCLK

I/O

B4

I/O

B5

I/O

B6

I/O

B7

I/O

V_CCI

GND

NC

GND

I/O

B8

I/O

B9

I/O

B10

I/O

B11

I/O

D2

I/O

B12

PRA, I/O

CLKA

I/O

D3

I/O

GND

I/O

B13

D4

TCK, I/O

I/O

B14

D5

I/O

GND

V_CCI

NC

B15

I/O

D6

I/O

AC2

B16

I/O

D7

I/O

AC3

B17

I/O

D8

I/O

AC4

I/O

B18

I/O

D9

I/O

AC5

I/O

B19

I/O

D10

I/O

v5.3

3-15

SX-A Family FPGAs

329-Pin PBGA

Number

A54SX32A

Number

A54SX32A

Function

A54SX32A

Function

A54SX32A

Function

V_CCA

NC

I/O

Number

L14

L20

L21

L22

L23

M1

Number

P12

P13

P14

P20

P21

P22

P23

R1

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

E1

H1

I/O

GND

NC

GND

I/O

H2

H3

I/O

H4

I/O

H20

H21

H22

H23

J1

V_CCA

I/O

NC

I/O

M2

I/O

M3

I/O

NC

M4

V_CCA

GND

V_CCA

I/O

R2

I/O

J2

I/O

M10

M11

M12

M13

M14

M20

M21

M22

M23

N1

R3

I/O

J3

I/O

R4

I/O

J4

I/O

R20

R21

R22

R23

T1

I/O

J20

J21

J22

J23

K1

I/O

V_CCI

I/O

E2

I/O

E3

I/O

E4

I/O

T2

I/O

E20

E21

E22

E23

F1

I/O

K2

I/O

V_CCI

I/O

T3

I/O

K3

I/O

T4

I/O

K4

I/O

N2

TRST, I/O

I/O

T20

T21

T22

T23

U1

I/O

K10

K11

K12

K13

K14

K20

K21

K22

K23

L1

GND

I/O

N3

I/O

N4

I/O

F2

TMS

I/O

N10

N11

N12

N13

N14

N20

N21

N22

N23

P1

GND

NC

I/O

F3

I/O

F4

I/O

U2

I/O

F20

F21

F22

F23

G1

I/O

U3

V_CCA

I/O

U4

I/O

U20

U21

U22

U23

V1

I/O

V_CCA

I/O

G2

I/O

L2

I/O

G3

I/O

L3

I/O

V_CCI

I/O

G4

I/O

L4

NC

P2

I/O

V2

G20

G21

G22

G23

I/O

L10

L11

L12

L13

GND

P3

I/O

V3

I/O

P4

I/O

V4

I/O

P10

P11

GND

V20

V21

I/O

GND

I/O

3-16

v5.3

SX-A Family FPGAs

329-Pin PBGA

A54SX32A

Function

Number

V22

V23

W1

I/O

NC

I/O

GND

I/O

V_CCA

NC

I/O

GND

I/O

W2

W3

W4

W20

W21

W22

W23

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

v5.3

3-17

SX-A Family FPGAs

144-Pin FBGA

4

1

2

3

5

6

7

8

10 11 12

9

A

B

C

D

E

F

G

H

J

K

L

M

Figure 3-6 • 144-Pin FBGA (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-18

v5.3

SX-A Family FPGAs

144-Pin FBGA

A54SX08A A54SX16A

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

A54SX32A

Function

Pin Number

A1

Pin Number

D1

Function

I/O

V_CCI

TDI, I/O

I/O

A2

I/O

D2

V_CCI

TDI, I/O

I/O

V_CCI

TDI, I/O

I/O

A3

I/O

D3

A4

I/O

D4

A5

V_CCA

GND

CLKA

I/O

V_CCA

GND

CLKA

I/O

V_CCA

GND

CLKA

I/O

D5

I/O

A6

D6

I/O

A7

D7

I/O

A8

D8

I/O

A9

I/O

D9

I/O

A10

A11

A12

B1

I/O

D10

D11

D12

E1

I/O

B2

GND

I/O

GND

I/O

GND

I/O

E2

I/O

B3

E3

I/O

B4

I/O

E4

I/O

B5

I/O

E5

TMS

V_CCI

V_CCA

I/O

TMS

V_CCI

V_CCA

I/O

TMS

V_CCI

V_CCA

I/O

B6

I/O

E6

B7

CLKB

I/O

CLKB

I/O

CLKB

I/O

E7

B8

E8

B9

I/O

E9

B10

B11

B12

C1

I/O

E10

E11

E12

F1

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

C2

I/O

F2

I/O

C3

TCK, I/O

I/O

TCK, I/O

I/O

TCK, I/O

I/O

F3

NC

C4

F4

I/O

C5

I/O

F5

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

C6

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

I/O

F6

C7

F7

C8

I/O

F8

C9

I/O

F9

C10

C11

C12

I/O

F10

F11

F12

GND

I/O

GND

I/O

GND

I/O

v5.3

3-19

SX-A Family FPGAs

144-Pin FBGA

A54SX08A A54SX16A

144-Pin FBGA

A54SX32A

Function

A54SX08A

Function

A54SX16A

Function

A54SX32A

Function

Pin Number

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

H1

Function

Pin Number

K1

I/O

GND

I/O

GND

I/O

GND

I/O

K2

I/O

K3

I/O

K4

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

GND

V_CCI

I/O

K5

I/O

K6

I/O

K7

GND

I/O

GND

I/O

GND

I/O

K8

K9

I/O

K10

K11

K12

L1

GND

I/O

GND

I/O

GND

I/O

TRST, I/O

I/O

TRST, I/O

I/O

TRST, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

H2

L2

H3

I/O

L3

I/O

H4

I/O

L4

I/O

H5

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

V_CCA

I/O

V_CCA

V_CCI

V_CCA

I/O

L5

I/O

H6

L6

I/O

H7

L7

HCLK

I/O

HCLK

I/O

HCLK

I/O

H8

L8

H9

L9

I/O

H10

H11

H12

J1

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

I/O

NC

I/O

J2

I/O

J3

I/O

J4

I/O

J5

I/O

J6

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

J7

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

J8

I/O

J9

I/O

J10

J11

J12

I/O

TDO, I/O

I/O

TDO, I/O

I/O

TDO, I/O

I/O

V_CCA

3-20

v5.3

SX-A Family FPGAs

256-Pin FBGA

1

2

3

4

6

7

8

9 10 11 12

13 14

5

15 16

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Figure 3-7 • 256-Pin FBGA (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

v5.3

3-21

SX-A Family FPGAs

256-Pin FBGA

A54SX16A A54SX32A

256-Pin FBGA

A54SX72A

Function

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

A1

Function

GND

TCK, I/O

I/O

Function

GND

TCK, I/O

I/O

Pin Number

C6

GND

TCK, I/O

I/O

A2

C7

I/O

A3

C8

I/O

A4

I/O

C9

CLKA

I/O

CLKA

I/O

CLKA

I/O

A5

I/O

C10

C11

C12

C13

C14

C15

C16

D1

A6

I/O

A7

I/O

A8

I/O

A9

CLKB

I/O

CLKB

I/O

CLKB

I/O

A10

A11

A12

A13

A14

A15

A16

B1

I/O

NC

I/O

D2

I/O

D3

I/O

GND

I/O

GND

I/O

GND

I/O

D4

I/O

D5

I/O

D6

I/O

B2

GND

I/O

GND

I/O

GND

I/O

D7

I/O

B3

D8

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

QCLKD

I/O

B4

I/O

D9

B5

I/O

D10

D11

D12

D13

D14

D15

D16

E1

I/O

B6

NC

I/O

NC

I/O

B7

I/O

B8

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

B9

I/O

B10

B11

B12

B13

B14

B15

B16

C1

I/O

NC

I/O

E2

I/O

E3

I/O

GND

I/O

GND

I/O

GND

I/O

E4

I/O

E5

I/O

E6

I/O

C2

TDI, I/O

GND

I/O

TDI, I/O

GND

I/O

TDI, I/O

GND

I/O

E7

I/O

QCLKC

I/O

C3

E8

I/O

C4

E9

I/O

C5

NC

I/O

E10

I/O

3-22

v5.3

SX-A Family FPGAs

256-Pin FBGA

A54SX16A A54SX32A

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

A54SX72A

Function

Pin Number

E11

E12

E13

E14

E15

E16

F1

Pin Number

G16

H1

Function

I/O

NC

I/O

H2

I/O

H3

V_CCA

TRST, I/O

I/O

V_CCA

TRST, I/O

I/O

V_CCA

TRST, I/O

I/O

H4

I/O

H5

I/O

H6

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

F2

I/O

H7

F3

I/O

H8

F4

TMS

I/O

TMS

I/O

TMS

I/O

H9

F5

H10

H11

H12

H13

H14

H15

H16

J1

F6

I/O

F7

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

F8

I/O

F9

I/O

F10

F11

F12

F13

F14

F15

F16

G1

I/O

NC

I/O

VCCA

I/O

VCCA

I/O

VCCA

I/O

NC

I/O

J2

NC

I/O

J3

NC

I/O

J4

I/O

J5

I/O

NC

I/O

J6

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

G2

I/O

J7

G3

NC

I/O

J8

G4

I/O

J9

G5

I/O

J10

J11

J12

J13

J14

J15

J16

K1

G6

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

G7

G8

I/O

G9

I/O

G10

G11

G12

G13

G14

G15

I/O

GND

NC

GND

I/O

GND

I/O

K2

I/O

K3

NC

I/O

V_CCA

K4

V_CCA

v5.3

3-23

SX-A Family FPGAs

256-Pin FBGA

A54SX16A A54SX32A

256-Pin FBGA

A54SX72A

Function

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

K5

Function

Pin Number

M10

M11

M12

M13

M14

M15

M16

N1

I/O

V_CCI

GND

V_CCI

I/O

GND

I/O

V_CCA

I/O

GND

I/O

V_CCA

I/O

K6

V_CCI

GND

V_CCI

I/O

V_CCI

GND

V_CCI

I/O

K7

NC

I/O

K8

K9

NC

I/O

K10

K11

K12

K13

K14

K15

K16

L1

I/O

N2

I/O

N3

I/O

NC

I/O

N4

I/O

N5

I/O

N6

I/O

L2

I/O

N7

I/O

L3

I/O

N8

I/O

L4

I/O

N9

I/O

L5

I/O

N10

N11

N12

N13

N14

N15

N16

P1

I/O

L6

I/O

L7

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

L8

I/O

L9

I/O

L10

L11

L12

L13

L14

L15

L16

M1

M2

M3

M4

M5

M6

M7

M8

M9

I/O

P2

GND

I/O

P3

I/O

P4

I/O

NC

I/O

P5

NC

I/O

P6

I/O

P7

I/O

P8

I/O

P9

I/O

P10

P11

P12

P13

P14

NC

I/O

QCLKA

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

V_CCA

I/O

3-24

v5.3

SX-A Family FPGAs

256-Pin FBGA

A54SX16A

Function

A54SX32A

Function

A54SX72A

Function

Pin Number

P15

P16

R1

I/O

R2

GND

I/O

GND

I/O

GND

I/O

R3

R4

NC

I/O

R5

I/O

R6

I/O

R7

I/O

R8

I/O

R9

HCLK

I/O

HCLK

I/O

HCLK

QCLKB

I/O

R10

R11

R12

R13

R14

R15

R16

T1

I/O

GND

I/O

GND

I/O

GND

I/O

T2

T3

I/O

T4

NC

I/O

T5

I/O

T6

I/O

T7

I/O

T8

I/O

T9

V_CCA

I/O

V_CCA

I/O

V_CCA

I/O

T10

T11

T12

T13

T14

T15

T16

I/O

NC

I/O

TDO, I/O

GND

TDO, I/O

GND

TDO, I/O

GND

v5.3

3-25

SX-A Family FPGAs

484-Pin FBGA

1

3 4 5 6 7 8 9 10 11121314 15161718 19 20212223 242526

2

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

Figure 3-8 • 484-Pin FBGA (Top View)

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.actel.com/products/rescenter/package/index.html.

3-26

v5.3

SX-A Family FPGAs

484-Pin FBGA

A54SX32A A54SX72A

Number

Function

NC*

I/O

Function

NC

I/O

Number

Function

NC*

V_CCI

I/O

Function

Number

Function

A1

A2

AA26

AB1

I/O

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

I/O

NC

I/O

A3

AB2

V_CCI

I/O

A4

I/O

AB3

I/O

QCLKA

I/O

A5

I/O

AB4

I/O

A6

I/O

AB5

NC*

I/O

A7

I/O

AB6

I/O

A8

I/O

AB7

I/O

A9

I/O

AB8

I/O

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

AA1

AA2

AA3

AA4

AA5

AA22

AA23

AA24

AA25

I/O

AB9

I/O

NC*

I/O

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

I/O

V_CCI

I/O

V_CCI

I/O

PRB, I/O

V_CCA

I/O

PRB, I/O

V_CCA

I/O

NC*

I/O

NC

I/O

NC*

I/O

NC*

I/O

AD2

I/O

NC*

V_CCA

I/O

TDO, I/O

GND

NC*

I/O

TDO, I/O

GND

I/O

AD3

GND

I/O

GND

I/O

AD4

I/O

AD5

I/O

AD6

I/O

NC

I/O

AD7

I/O

NC*

I/O

AD8

I/O

AD9

V_CCI

I/O

V_CCI

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

V_CCA

I/O

AC2

I/O

AC3

I/O

AC4

NC*

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

AC5

V_CCI

I/O

AC6

I/O

AC7

V_CCI

I/O

V_CCI

I/O

NC*

I/O

AC8

V_CCI

Note: *These pins must be left floating on the A54SX32A device.

v5.3

3-27

SX-A Family FPGAs

484-Pin FBGA

A54SX32A A54SX72A

484-Pin FBGA

A54SX32A A54SX72A

Number

Function

I/O

V_CCI

I/O

NC

I/O

NC

Number

Function

NC*

NC

Function

NC

I/O

Number

Function

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

I/O

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

B1

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

I/O

NC*

V_CCI

CLKA

NC*

I/O

NC*

I/O

V_CCI

CLKA

I/O

V_CCI

NC*

I/O

V_CCI

I/O

V_CCI

I/O

AE2

NC*

HCLK

I/O

AE3

NC*

I/O

NC

HCLK

QCLKB

I/O

NC*

I/O

AE4

I/O

AE5

I/O

AE6

NC*

I/O

AE7

I/O

AE8

I/O

NC*

I/O

NC

AE9

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

I/O

C2

I/O

NC*

I/O

NC*

I/O

C3

I/O

C4

I/O

C5

I/O

C6

V_CCI

I/O

V_CCI

I/O

NC*

I/O

C7

NC

I/O

C8

I/O

C9

V_CCI

I/O

V_CCI

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

I/O

B2

I/O

B3

I/O

NC*

B4

I/O

PRA, I/O

I/O

PRA, I/O

I/O

B5

I/O

B6

I/O

QCLKD

I/O

B7

I/O

B8

I/O

B9

I/O

Note: *These pins must be left floating on the A54SX32A device.

3-28

v5.3

SX-A Family FPGAs

484-Pin FBGA

A54SX32A A54SX72A

Number

Function

Number

Function

NC*

I/O

Function

Number

Function

NC*

I/O

Function

C19

C20

C21

C22

C23

C24

C25

C26

D1

I/O

E2

E3

I/O

G1

G2

G3

G4

G5

G22

G23

G24

G25

G26

H1

I/O

V_CCI

I/O

V_CCI

I/O

E4

I/O

E5

GND

TDI, IO

I/O

GND

TDI, IO

I/O

E6

I/O

E7

I/O

NC*

TMS

I/O

E8

I/O

V_CCA

I/O

V_CCA

I/O

E9

I/O

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

I/O

NC*

I/O

D2

TMS

I/O

D3

I/O

D4

V_CCI

NC*

TCK, I/O

I/O

V_CCI

I/O

V_CCA

CLKB

I/O

V_CCA

CLKB

I/O

H2

I/O

D5

H3

I/O

D6

TCK, I/O

I/O

H4

I/O

D7

I/O

H5

I/O

D8

I/O

H22

H23

H24

H25

H26

J1

I/O

D9

I/O

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

I/O

NC*

I/O

QCLKC

I/O

J2

I/O

J3

I/O

V_CCI

GND

V_CCI

NC*

I/O

V_CCI

GND

V_CCI

I/O

J4

I/O

J5

I/O

J22

J23

J24

J25

J26

K1

I/O

F2

I/O

F3

I/O

V_CCI

GND

I/O

V_CCI

GND

I/O

F4

I/O

V_CCI

NC*

I/O

V_CCI

I/O

F5

I/O

F22

F23

F24

F25

F26

I/O

K2

V_CCI

I/O

V_CCI

I/O

NC*

I/O

K3

I/O

K4

I/O

NC*

I/O

K5

V_CCA

Note: *These pins must be left floating on the A54SX32A device.

v5.3

3-29

SX-A Family FPGAs

484-Pin FBGA

A54SX32A A54SX72A

484-Pin FBGA

A54SX32A A54SX72A

Number

Function

GND

I/O

Function

GND

I/O

Number

Function

Number

Function

K10

K11

K12

K13

K14

K15

K16

K17

K22

K23

K24

K25

K26

L1

M5

M10

M11

M12

M13

M14

M15

M16

M17

M22

M23

M24

M25

M26

N1

I/O

P4

I/O

GND

I/O

GND

I/O

P5

V_CCA

GND

I/O

V_CCA

GND

I/O

P10

P11

P12

P13

P14

P15

P16

P17

P22

P23

P24

P25

P26

R1

I/O

NC*

I/O

NC

I/O

NC*

I/O

V_CCI

I/O

V_CCI

I/O

L2

I/O

L3

I/O

N2

V_CCI

I/O

V_CCI

I/O

NC*

I/O

L4

I/O

N3

R2

I/O

L5

I/O

N4

I/O

R3

I/O

L10

L11

L12

L13

L14

L15

L16

L17

L22

L23

L24

L25

L26

M1

M2

M3

M4

GND

I/O

GND

I/O

N5

I/O

R4

I/O

N10

N11

N12

N13

N14

N15

N16

N17

N22

N23

N24

N25

N26

P1

GND

V_CCA

I/O

GND

V_CCA

I/O

R5

TRST, I/O

GND

I/O

TRST, I/O

GND

I/O

R10

R11

R12

R13

R14

R15

R16

R17

R22

R23

R24

R25

R26

T1

I/O

NC*

I/O

NC

NC*

I/O

NC

NC*

I/O

P2

I/O

P3

I/O

T2

I/O

Note: *These pins must be left floating on the A54SX32A device.

3-30

v5.3

SX-A Family FPGAs

484-Pin FBGA

A54SX32A A54SX72A

Number

Function

Number

Function

NC*

I/O

Function

T3

I/O

V2

V3

I/O

T4

I/O

T5

I/O

V4

I/O

T10

T11

T12

T13

T14

T15

T16

T17

T22

T23

T24

T25

T26

U1

GND

I/O

GND

I/O

V5

I/O

V22

V23

V24

V25

V26

W1

W2

W3

W4

W5

W22

W23

W24

W25

W26

Y1

V_CCA

I/O

V_CCA

I/O

NC*

I/O

NC*

I/O

V_CCA

I/O

V_CCA

I/O

U2

V_CCI

I/O

V_CCI

I/O

NC*

I/O

U3

I/O

U4

I/O

U5

I/O

Y2

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U22

U23

U24

U25

U26

V1

GND

I/O

GND

I/O

Y3

I/O

Y4

I/O

Y5

NC*

I/O

Y22

Y23

Y24

Y25

Y26

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

V_CCI

I/O

NC*

I/O

Note: *These pins must be left floating on the A54SX32A device.

v5.3

3-31

SX-A Family FPGAs

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v5.3)

Page

N/A

2-14

ii

v5.2

–3 speed grades have been discontinued.

(June 2006)

The "SX-A Timing Model" was updated with –2 data.

RoHS information was added to the "Ordering Information".

The "Programming" section was updated.

v5.1

February 2005

v5.0

1-13

Revised Table 1 and the timing data to reflect the phase out of the –3 speed grade for the

A54SX08A device.

i

The "Thermal Characteristics" section was updated.

The "176-Pin TQFP" was updated to add pins 81 to 90.

The "484-Pin FBGA" was updated to add pins R4 to Y26

The "Temperature Grade Offering" is new.

The "Speed Grade and Temperature Grade Matrix" is new.

"SX-A Family Architecture" was updated.

"Clock Resources" was updated.

"User Security" was updated.

2-11

3-11

3-26

1-iii

1-1

v4.0

1-5

1-7

"Power-Up/Down and Hot Swapping" was updated.

"Dedicated Mode" is new

1-7

1-9

Table 1-5 is new.

1-9

"JTAG Instructions" is new

1-10

1-12

1-13

1-15

2-1

"Design Considerations" was updated.

The "Programming" section is new.

"Design Environment" was updated.

"Pin Description" was updated.

Table 2-1 was updated.

Table 2-2 was updated.

2-1

Table 2-3 is new.

2-1

Table 2-4 is new.

2-1

Table 2-5 was updated.

2-2

Table 2-6 was updated.

2-2

"Power Dissipation" is new.

2-8

Table 2-11 was updated.

2-9

v5.3

4-1

SX-A Family FPGAs

Previous Version Changes in Current Version (v5.3)

Page

2-11

2-14

2-17

v4.0

Table 2-12 was updated.

(continued)

The was updated.

The "Sample Path Calculations" were updated.

Table 2-13 was updated.

All timing tables were updated.

2-18 to

2-52

v3.0

The "Actel Secure Programming Technology with FuseLock™ Prevents Reverse Engineering and 1-i

Design Theft" section was updated.

The "Ordering Information" section was updated.

1-ii

The "Temperature Grade Offering" section was updated.

The Figure 1-1 • SX-A Family Interconnect Elements was updated.

The “"Clock Resources" section“was updated

1-iii

1-1

1-5

The Table 1-1 • SX-A Clock Resources is new.

1-5

The "User Security" section is new.

1-7

The "I/O Modules" section was updated.

1-7

The Table 1-2 • I/O Features was updated.

1-8

The Table 1-3 • I/O Characteristics for All I/O Configurations is new.

The Table 1-4 • Power-Up Time at which I/Os Become Active is new

The Figure 1-12 • Device Selection Wizard is new.

1-8

1-9

The "Boundary-Scan Pin Configurations and Functions" section is new.

The Table 1-9 • Device Configuration Options for Probe Capability (TRST Pin Reserved) is new.

The "SX-A Probe Circuit Control Pins" section was updated.

The "Design Considerations" section was updated.

1-9

1-11

1-12

1-13

1-11

1-12

1-13

1-23

1-15

1-13

1-8

The Figure 1-13 • Probe Setup was updated.

The Design Environment was updated.

The Figure 1-13 • Design Flow is new.

The "Absolute Maximum Ratings*" section was updated.

The "Recommended Operating Conditions" section was updated.

The "Electrical Specifications" section was updated.

The "2.5V LVCMOS2 Electrical Specifications" section was updated.

The "SX-A Timing Model" and "Sample Path Calculations" equations were updated.

The "Pin Description" section was updated.

v2.0.1

The "Design Environment" section has been updated.

The "I/O Modules" section, and Table 1-2 • I/O Features have been updated.

The "SX-A Timing Model" section and the "Timing Characteristics" section have new timing 1-23

numbers.

4-2

v5.3

SX-A Family FPGAs

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet

Supplement." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advanced or production) containing general product

information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

International Traffic in Arms Regulations (ITAR) and Export

Administration Regulations (EAR)

The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the

Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export

can include a release or disclosure to a foreign national inside or outside the United States.

v5.3

4-3

Actel and the Actel logo are registered trademarks of Actel Corporation.

All other trademarks are the property of their owners.

www.actel.com

Actel Corporation

Actel Europe Ltd.

Actel Hong Kong

Actel Japan

2061 Stierlin Court

Mountain View, CA

94043-4655 USA

River Court, Meadows Business Park

Station Approach, Blackwater

Camberley, Surrey GU17 9AB

United Kingdom

Suite 2114, Two Pacific Place

88 Queensway, Admiralty

Hong Kong

EXOS Ebisu Bldg. 4F

1-24-14 Ebisu Shibuya-ku

Tokyo 150 Japan

Phone 650.318.4200

Fax 650.318.4600

Phone +852 2185 6460

Fax +852 2185 6488

www.actel.com.cn

Phone +81.03.3445.7671

Fax +81.03.3445.7668

www.jp.actel.com

Phone +44 (0) 1276 609 300

Fax +44 (0) 1276 607 540

5172147-10/2.07

型号：	A54SX16A-2PQG208I
PDF下载：	下载PDF文件查看货源
内容描述：	SX -A系列FPGA [SX-A Family FPGAs]
分类和应用：	现场可编程门阵列可编程逻辑栅时钟
文件页数/大小：	108 页 / 828 K
品牌：	ACTEL [ Actel Corporation ]

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