SX-A Family FPGAs
Output Buffer Delays
E
D
TRIBUFF
PAD
To AC Test Loads (shown below)
V
CC
In
Out
V
OL
t
DLH
Figure 2-4 •
Output Buffer Delays
V
CC
GND
1.5 V
En
Out
50% 50%
V
CC
1.5 V
V
OL
t
ENZL
GND
10%
t
ENLZ
En
Out
GND
V
CC
50%
50%
1.5 V
t
ENZH
t
ENHZ
GND
90%
50% 50%
V
OH
1.5 V
AC Test Loads
Load 1
(Used to measure
propagation delay)
To the Output
Under Test
35 pF
Load 2
(Used to measure enable delays)
V
CC
GND
R to V
CC
for t
PZL
R to GND for t
PZH
R = 1 kΩ
35 pF
Load 3
(Used to measure disable delays)
V
CC
GND
R to V
CC
for tPZL
R to GND for tPZH
R = 1 kΩ
5 pF
To the Output
Under Test
To the Output
Under Test
Figure 2-5 •
AC Test Loads
v5.3
2-15