v2.0
HiRel SX-A Family FPGAs
Features and Benefits
Leading Edge Performance
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215 MHz System Performance (Military Temperature)
5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
240 MHz Internal Performance (Military Temperature)
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Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and Design
Theft
Cold-Sparing Capability
Individual Output Slew Rate Control
QML Certified Devices
100% Military Temperature Tested (–55°C to +125°C)
33 MHz PCI Compliant
CPLD and FPGA Integration
Single-Chip Solution
Configurable I/O Support for 3.3 V/5 V PCI, LVTTL,
and TTL
Configurable Weak Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power-Up
Up to 100% Resource Utilization and 100% Pin
Locking
2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary-Scan Testing in Compliance with IEEE
1149.1 (JTAG)
A54SX32A
32,000
48,000
2,880
1,800
1,080
1,980
228
3
0
Yes
Yes
5.3 ns
0 ns
Std, –1
84, 208, 256
A54SX72A
72,000
108,000
6,036
4,024
2,012
4,024
213
3
4
Yes
Yes
6.7 ns
0 ns
Std, –1
208, 256
Specifications
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48,000 to 108,000 Available System Gates
Up to 228 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
0.25/0.22 µ CMOS Process Technology
Features
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Hot-Swap Compliant I/Os
Power-Up/Down Friendly (no sequencing required
for supply voltages)
Class B Level Devices
Three Standard Hermetic Package Options
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Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Maximum User I/Os
Global Clocks
Quadrant Clocks
Boundary-Scan Testing
3.3 V / 5 V PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Package (by Pin Count)
CQFP
N o ve m b e r 2 0 0 6
© 2006 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
ACTEL [ Actel Corporation ]
