IGLOO PLUS Low-Power Flash FPGAs
•
•
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL
only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
f
OUT_CCC
(for PLL only)
Global Clocking
IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC
and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
v1.3
1-7
ACTEL [ Actel Corporation ]
