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AGLP030-V2FCSG289ES 参数 Datasheet PDF下载

AGLP030-V2FCSG289ES图片预览
型号: AGLP030-V2FCSG289ES
PDF下载: 下载PDF文件 查看货源
内容描述: IGLOO PLUS低功耗闪存的FPGA快速冻结技术 [IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology]
分类和应用: 闪存
文件页数/大小: 14 页 / 526 K
品牌: ACTEL [ Actel Corporation ]
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v1.3
IGLOO PLUS Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low-Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW
State per I/O in Flash*Freeze Mode
• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode
®
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—4 Banks per Chip on All
IGLOO
®
PLUS Devices
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Selectable Schmitt Trigger Inputs
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Feature Rich
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
AGLP030
30 k
256
792
5
1k
6
4
120
CS201, CS289
VQ128
AGLP060
60 k
512
1,584
10
18
4
Yes
1k
1
18
4
157
CS201, CS289
VQ176
AGLP125
125 k
1,024
3,120
16
36
8
Yes
1k
1
18
4
212
CS281, CS289
Table 1-1 •
IGLOO PLUS Product Family
IGLOO PLUS Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
Secure (AES) ISP
FlashROM Bits
Integrated PLL in CCCs
1
VersaNet Globals
2
I/O Banks
Maximum User I/Os
Package Pins
CS
VQ
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
† The AGLP030 device does not support this feature.
December 2008
© 2008 Actel Corporation
I