ProASIC
PLUS
Flash Family FPGAs
High-Performance
Global Network
PAD RING
PAD RING
I/O RING
Top Spine
Global Networks
Global
Pads
Global
Pads
Global Spine
Global Ribs
Bottom Spine
I/O RING
Scope of Spine
(Shaded area
plus local RAMs
and I/Os)
PAD RING
Note:
This figure shows routing for only one global path.
Figure 1-7 •
High-Performance Global Network
Table 1-1 •
Clock Spines
APA075
Global Clock Networks (Trees)
Clock Spines/Tree
Total Spines
Top or Bottom Spine Height (Tiles)
Tiles in Each Top or Bottom Spine
Total Tiles
4
6
24
16
512
3,072
APA150
4
8
32
24
768
6,144
APA300
4
8
32
32
1,024
8,192
APA450
4
12
48
32
1,024
12,288
APA600
4
14
56
48
1,536
21,504
APA750
4
16
64
64
2,048
32,768
APA1000
4
22
88
80
2,560
56,320
v5.2
1-7
ACTEL [ Actel Corporation ]
