Automotive Supplement
Automotive-Grade ProASIC
PLUS
Flash Family FPGAs
Features and Benefits
High Capacity
•
•
•
•
•
•
•
75,000 to 1 Million System Gates
27k to 198kbits of Two-Port SRAM
66 to 642 User I/Os
0.22µ 4LM Flash-based CMOS Process
Live at Power-Up, Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during
Power-Down/Power-Up Cycles
Supports Automotive Temperature Range -40 to 125°C (Junction)
3.3V, 32-Bit PCI (up to 50 MHz)
Two Integrated PLLs
External System Performance up to 150 MHz
Industry’s Most Effective Security Key (FlashLock™)
Prevents Read Back of Programming Bitstream
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
Ultra-Fast Local and Long-Line Network
APA075
75,000
3,072
27k
12
2
2
4
24
158
Yes
Yes
100
208
144
APA150
150,000
6,144
36k
16
2
2
4
32
186
Yes
Yes
100
208
144, 256
APA300
300,000
8,192
72k
32
2
2
4
32
186
Yes
Yes
–
208
144, 256
APA450
450,000
12,288
108k
48
2
2
4
48
344
Yes
Yes
–
208
144, 256, 484
APA600
600,000
21,504
126k
56
2
2
4
56
370
Yes
Yes
–
208
256, 484
APA750
750,000
32,768
144k
64
2
2
4
64
562
Yes
Yes
–
208
896
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TM
High-Speed, Very Long-Line Network
High Performance, Low-Skew, Splittable Global Network
100% Utilization and >95% Routability
Schmitt-Trigger Option on Every Input
2.5V/3.3V Support with Individually-Selectable Voltage and
Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across ProASIC
PLUS
Family
PLLs with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Frontend Tools
Efficient Design through Front-End Timing and Gate
Optimization
In-System Programming (ISP) via JTAG Port
ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
I/O
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
Extended Temperature Range
•
•
•
•
•
Performance
Standard FPGA and ASIC Design Flow
Secure Programming
Low Power
•
•
•
ISP Support
•
•
•
SRAMs and FIFOs
High Performance Routing Hierarchy
•
Table 1 •
Automotive-Grade ProASIC
PLUS
Product Profile
Device
Maximum System Gates
Maximum Tiles (Registers)
Embedded RAM Bits (k=1,024
bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package
(by pin count)
TQFP
PQFP
FBGA
APA1000
1,000,000
56,320
198k
88
2
2
4
88
642
Yes
Yes
–
208
896
February 2004
© 2004 Actel Corporation
1
ACTEL [ Actel Corporation ]
