欢迎访问ic37.com |
会员登录 免费注册
发布采购

APA6001 参数 Datasheet PDF下载

APA6001图片预览
型号: APA6001
PDF下载: 下载PDF文件 查看货源
内容描述: 的ProASIC闪存系列FPGA [ProASIC Flash Family FPGAs]
分类和应用: 闪存
文件页数/大小: 178 页 / 5078 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号APA6001的Datasheet PDF文件第2页浏览型号APA6001的Datasheet PDF文件第3页浏览型号APA6001的Datasheet PDF文件第4页浏览型号APA6001的Datasheet PDF文件第5页浏览型号APA6001的Datasheet PDF文件第6页浏览型号APA6001的Datasheet PDF文件第7页浏览型号APA6001的Datasheet PDF文件第8页浏览型号APA6001的Datasheet PDF文件第9页  
v5.9
ProASIC
PLUS®
Flash Family FPGAs
High Performance Routing Hierarchy
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
®
Features and Benefits
High Capacity
Commercial and Industrial
75,000 to 1 Million System Gates
27 K to 198 Kbits of Two-Port SRAM
66 to 712 User I/Os
300, 000 to 1 Million System Gates
72 K to 198 Kbits of Two Port SRAM
158 to 712 User I/Os
0.22 µm 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
Two Integrated PLLs
External System Performance up to 150 MHz
The Industry’s Most Effective Security Key (FlashLock
®
)
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
APA075
75,000
3,072
27 k
12
2
2
4
24
158
Yes
Yes
100, 144
208
144
APA150
150,000
6,144
36k
16
2
2
4
32
242
Yes
Yes
100
208
456
144, 256
I/O
Schmitt-Trigger Option on Every Input
2.5 V / 3.3 V Support with Individually-Selectable Voltage
and Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin-Compatible Packages across the ProASIC
PLUS
Family
PLL with Flexible Phase, Multiply/Divide, and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate
Optimization
In-System Programming (ISP) via JTAG Port
SmartGen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
Military
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
Standard FPGA and ASIC Design Flow
Performance
ISP Support
Secure Programming
Low Power
SRAMs and FIFOs
Table 1 •
ProASIC
PLUS
Product Profile
Device
Maximum System Gates
Tiles (Registers)
Embedded RAM Bits (k=1,024 bits)
Embedded RAM Blocks (256x9)
LVPECL
PLL
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
PCI
Package (by pin count)
TQFP
PQFP
PBGA
FBGA
CQFP
2
CCGA/LGA
2
Notes:
APA300
1
300,000
8,192
72 k
32
2
2
4
32
290
Yes
Yes
208
456
144, 256
208, 352
APA450
450,000
12,288
108 k
48
2
2
4
48
344
Yes
Yes
208
456
144, 256, 484
APA600
1
600,000
21,504
126 k
56
2
2
4
56
454
Yes
Yes
208
456
256, 484, 676
208, 352
624
APA750
750,000
32,768
144 k
64
2
2
4
64
562
Yes
Yes
208
456
676, 896
APA1000
1
1,000,000
56,320
198 k
88
2
2
4
88
712
Yes
Yes
208
456
896, 1152
208, 352
624
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
D e c e m b er 2 0 0 9
© 2009 Actel Corporation
i
See the Actel website for the latest version of the datasheet.