ProASIC
PLUS
Flash Family FPGAs
Design Environment
The ProASIC
PLUS
family of FPGAs is fully supported by
both Actel's Libero
®
Integrated Design Environment
(IDE) and Designer FPGA Development software. Actel
Libero IDE is an integrated design manager that
seamlessly integrates design tools while guiding the user
through the design flow, managing all design and log
files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment (see Actel’s
website for more information about
Libero
IDE includes Synplify
®
AE from Synplicity®, ViewDraw
®
AE from Mentor Graphics
®
, ModelSim
®
HDL Simulator
from Mentor Graphics, WaveFormer Lite™ AE from
SynaptiCAD
®
, PALACE™ AE Physical Synthesis from
Magma, and Designer software from Actel.
PALACE is an effective tool when designing with
ProASIC
PLUS
. PALACE AE Physical Synthesis from Magma
takes an EDIF netlist and optimizes the performance of
ProASIC
PLUS
devices through a physical placement-driven
process, ensuring that timing closure is easily achieved.
Actel's Designer software is a place-and-route tool that
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
•
Timer – A world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
NetlistViewer – A design netlist schematic viewer
ChipPlanner – A graphical floorplanner viewer and
editor
SmartPower – Allows the designer to quickly
estimate the power consumption of a design
PinEditor – A graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor – Displays all assigned and
unassigned I/O macros and their attributes in a
spreadsheet format
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel’s back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the SmartGen
macro builder, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
ISP
The user can generate *.bit or *.stp programming files
from the Designer software and can use these files to
program a device.
ProASIC
PLUS
devices can be programmed in-system. For
more information on ISP of ProASIC
PLUS
devices, refer to
the
and
ProASIC
PLUS
Devices
application notes. Prior to being
programmed for the first time, the ProASIC
PLUS
device I/Os
are in a tristate condition with the pull-up resistor option
enabled.
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v5.9
2-25
ACTEL [ Actel Corporation ]
