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AX1000-2FGG896I 参数 Datasheet PDF下载

AX1000-2FGG896I图片预览
型号: AX1000-2FGG896I
PDF下载: 下载PDF文件 查看货源
内容描述: 的Axcelerator系列FPGA [Axcelerator Family FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 226 页 / 2293 K
品牌: ACTEL [ Actel Corporation ]
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v2.7
Axcelerator Family FPGAs
u e
Leading-Edge Performance
350+ MHz System Performance
500+ MHz Internal Performance
High-Performance Embedded FIFOs
700 Mb/s LVDS Capable I/Os
Up to 2 Million Equivalent System Gates
Up to 684 I/Os
Up to 10,752 Dedicated Flip-Flops
Up to 295 kbits Embedded SRAM/FIFO
Manufactured on Advanced 0.15
μm
CMOS Antifuse
Process Technology, 7 Layers of Metal
Single-Chip, Nonvolatile Solution
Up to 100% Resource Utilization with 100% Pin Locking
1.5V Core Voltage for Low Power
Footprint Compatible Packaging
Flexible, Multi-Standard I/Os:
– 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation
– Bank-Selectable I/Os – 8 Banks per Chip
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V
PCI, and 3.3V PCI-X
– Differential I/O Standards: LVPECL and LVDS
AX125
125,000
82,000
672
1,344
1,344
4
18,432
4
4
8
8
168
84
504
180
Specifications
Features
Voltage-Referenced I/O Standards: GTL+, HSTL
Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
– Registered I/Os
– Hot-Swap Compliant I/Os (except PCI)
– Programmable Slew Rate and Drive Strength on
Outputs
– Programmable Delay and Weak Pull-Up/Pull-Down
Circuits on Inputs
Embedded Memory:
– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18, x36 Organizations Available)
– Independent, Width-Configurable Read and Write Ports
– Programmable Embedded FIFO Control Logic
Segmentable Clock Resources
Embedded Phase-Locked Loop:
– 14-200 MHz Input Range
– Frequency Synthesis Capabilities up to 1 GHz
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
with Actel Silicon Explorer II
Boundary-Scan Testing Compliant with IEEE Standard
1149.1 (JTAG)
FuseLock
TM
Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Table 1-1 •
Axcelerator Family Product Profile
Device
Capacity (in Equivalent System Gates)
Typical Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Maximum Flip-Flops
Embedded RAM/FIFO
Number of Core RAM Blocks
Total Bits of Core RAM
Clocks (Segmentable)
Hardwired
Routed
PLLs
I/Os
I/O Banks
Maximum User I/Os
Maximum LVDS Channels
Total I/O Registers
Package
CSP
PQFP
BGA
FBGA
CQFP
CCGA
AX250
250,000
154,000
1,408
2,816
2,816
12
55,296
4
4
8
8
248
124
744
AX500
500,000
286,000
2,688
5,376
5,376
16
73,728
4
4
8
8
336
168
1,008
AX1000
1,000,000
612,000
6,048
12,096
12,096
36
165,888
4
4
8
8
516
258
1,548
AX2000
2,000,000
1,060,000
10,752
21,504
21,504
64
294,912
4
4
8
8
684
342
2,052
208
256, 324
256, 484
208, 352
208
484, 676
208, 352
729
484, 676, 896
352
624
896, 1152
352
624
November 2008
© 2008 Actel Corporation
i
*See Actel’s website for the latest version of the datasheet.