ARINC 429 Bus Interface
Product Summary
Intended Use
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ARINC 429 Transmitter (Tx)
ARINC 429 Receiver (Rx)
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Core Deliverables
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Evaluation Version
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Compiled RTL Simulation Model, Compliant
with the Actel Libero
®
Integrated Design
Environment (IDE)
Structural VHDL and Verilog Netlists
VHDL or Verilog Core Source Code
Synthesis Scripts
Netlist Version
RTL version
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Key Features
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Supports ARINC Specification 429-16
Configurable up to 16 Rx and 16 Tx Channels
Programmable FIFO Depth
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Up to 512 Words
Rx and Tx Channels independently
Up to 64 Words
Programmable Interrupt Generation
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Verification Testbench – Verilog
User Testbenches
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Libero IDE Compatible
VHDL and Verilog
Configurable Label Memory Size
Rx and Tx Channels independently
Up to 256 Words
Development System
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Complete ARINC 429 Rx/Tx
Implementation
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Implemented in an APA600 Device
Controlled Via an External Terminal Using
Core8051 and RS232 Links
Internal, Wrap-Around Testing
Software Compatible with Legacy Devices
Selectable Clock Speed
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1, 10, 16, or 20 MHz
12.5 100 kbps
Optional 50 kbps
Provides Direct CPU Access to Memory
Simple Interface to Core8051
EDAC Support with RTAX-S Family
Supports Standard Line Drivers and Receivers
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Selectable Data Rate on Each Channel
Includes Line Driver and Receiver Components
Synthesis and Simulation Support
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Directly Supported within the Actel Libero IDE
Synthesis:
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Synplicity®
Exemplar
TM
Synopsys
®
Vital-Compliant VHDL Simulators
OVI-Compliant Verilog Simulators
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CPU Interface
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Memory
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ARINC 429 Bus Interface
Available as Integrated Tx and Rx
Simulation
Supported Families
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Fusion
ProASIC
®
3/E
ProASIC
PLUS®
Axcelerator
®
RTAX-S
Verification and Compliance
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Actel-Developed Simulation Testbench
Core
Implemented
Development System
on
the
ARINC
429
September 2006
© 2006 Actel Corporation
v 5 .0
1
ACTEL [ Actel Corporation ]
