CoreDES
Product Summary
Intended Use
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•
Whenever Data is Transmitted across an Accessible
Medium (Wires, Wireless, etc.)
E-Commerce Transactions, where Dedicated
Encryption/Decryption Hardware Can Ease the
Load on Servers
Personal Security Devices
Bank Transactions, where Financial Security is
Mandatory
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Core Deliverables
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Evaluation Version
–
Compiled RTL Simulation Model Fully
Supported in the Actel Libero
®
Integrated
Design Environment (IDE)
Structural Verilog and VHDL Netlists (with and
without I/O pads) Compatible with the Actel
Designer Place-and-Route Software Tool
Compiled RTL Simulation Model
Supported in the Actel Libero IDE
Verilog or VHDL Core Source Code
Core Synthesis Scripts
Fully
Netlist Version
–
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–
RTL Version
–
–
Key Features
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56-bit Cipher Key (with 8 Additional Parity Bits)
Parity Checking Logic for Cipher Key
Encryption and Decryption Possible with Same
Core
16-Clock Cycle Operation to Encrypt or Decrypt 64
Bits of Data
Pause/Resume
Functionality
Encryption or Decryption at Will
Compliant with FIPS PUB 46-3
ECB (Electronic Codebook) Implementation per
FIPS PUB 81
Example Source Code Provided for CBC, CFB and
OFB Modes
Provides Data Security within a Secure Actel FPGA
All Major Actel Device Families Supported
•
to
Continue
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Actel-Developed Testbench (Verilog and VHDL)
Synthesis and Simulation Support
•
Synthesis:
Synplicity
®
,
Synopsys
®
(Design
®
Compiler / FPGA Compiler
™
/ FPGA Express
™
),
Exemplar
™
Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
•
Core Verification
•
Actel-Developed Simulation Testbench Verifies
CoreDES against Tests Listed in the National
Institute of Standards and Technology (NIST)
Special Publication 800-17,
Modes of Operation
Validation System (MOVS): Requirements and
Procedures
Users Can Easily Modify Testbench Using Existing
Format to Add More Tests Listed in NIST Special
Publication 800-17 or Custom Tests
Supported Families
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Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
SX-A
RTSX-S
December 2005
© 2005 Actel Corporation
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