CoreSDLC
Product Summary
Intended Use
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ISDN D-Channel
X.25 Networks
Frame Relay Networks
Custom Serial Interfaces
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Netlist Version
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Structural Verilog and VHDL Netlists (with and
without I/O pads) Compatible with Actel's
Designer Software Place-and-Route Tool
Compiled RTL Simulation
Supported in Actel Libero IDE
Model
Fully
RTL Version
Verilog and VHDL Core Source Code
Core Synthesis Scripts
Key Features
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Based on Intel's 80C152 Global Serial Channel
Working in SDLC Mode
Single and Double-Byte Address Recognition
Address Filtering Enables Multicast and Broadcast
Addresses
16-bit (CRC-16) and 32-bit (CRC-32) Frame Check
Sequence
NRZ and NRZI Data Encoding
Automatic Bit Stuffing/Stripping
3-Byte Deep Internal Receive and Transmit FIFOs
Full or Half-Duplex Operation
Variable Baud Rate
External or Internal Transmit and Receive Clocks
Optional Preamble Generation
Programmable Interframe Space
Raw Transmit and Receive Testing Modes
All Major Actel Device Families Supported
Testbench (Verilog and VHDL)
Synthesis and Simulation Support
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Synthesis: Synplicity
®
, Synopsys
®
(Design Compiler
®
/ FPGA Compiler
TM
/ FPGA Express
TM
), Exemplar
TM
Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Core Verification
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Comprehensive VHDL and Verilog Testbenches
User can Modify Testbench Using Existing Format
to Add Custom Tests
Contents
Supported Families
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Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
SX-A
RTSX-S
Core Deliverables
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Evaluation Version
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Compiled RTL Simulation Model Fully
Supported in Actel Libero
®
Integrated Design
Environment (IDE)
December 2005
© 2005 Actel Corporation
v 4 .0
1
ACTEL [ Actel Corporation ]
