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EX128-TQG100 参数 Datasheet PDF下载

EX128-TQG100图片预览
型号: EX128-TQG100
PDF下载: 下载PDF文件 查看货源
内容描述: 的eX系列FPGA [eX Family FPGAs]
分类和应用: 可编程逻辑时钟
文件页数/大小: 49 页 / 410 K
品牌: ACTEL [ Actel Corporation ]
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v4.3
eX Family FPGAs
FuseLock
Leading Edge Performance
240 MHz System Performance
350 MHz Internal Performance
3.9 ns Clock-to-Out (Pad-to-Pad)
Specifications
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22µm CMOS Process Technology
Up to 132 User-Programmable I/O Pins
Features
High-Performance, Low-Power Antifuse FPGA
LP/Sleep Mode for Additional Power Savings
Advanced Small-Footprint Packages
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
Live on Power-Up
No Power-Up/Down Sequence Required for Supply
Voltages
Configurable Weak-Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
Individual Output Slew Rate Control
2.5 V, 3.3 V, and 5.0 V Mixed-Voltage Operation
with 5.0V Input Tolerance and 5.0V Drive Strength
Software Design Support with Actel Designer and
Libero™ Integrated Design Environment (IDE)
Tools
Up to 100% Resource Utilization with 100% Pin
Locking
Deterministic Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Fuselock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Product Profile
Device
Capacity
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Combinatorial Cells
Maximum User I/Os
Global Clocks
Hardwired
Routed
Speed Grades
Temperature Grades*
Package
(by pin count)
TQFP
CSP
eX64
3,000
2,000
64
128
128
84
1
2
–F, Std, –P
C, I, A
64, 100
49, 128
eX128
6,000
4,000
128
256
256
100
1
2
–F, Std, –P
C, I, A
64, 100
49, 128
eX256
12,000
8,000
256
512
512
132
1
2
–F, Std, –P
C, I, A
100
128, 180
Note:
*Refer to the
datasheet for details on automotive temperature offerings.
June 2006
© 2006 Actel Corporation
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