v1.0
ProASIC3E Flash Family FPGAs
with Optional Soft ARM
®
Support
Features and Benefits
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
®
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay
• Schmitt Trigger Option on Single-Ended Inputs
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC
®
3E Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, Each with an Integrated PLL
• Configurable
Phase-Shift,
Multiply/Divide,
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 200 MHz)
Delay
Low Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
®
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
with or without Debug
High-Performance Routing Hierarchy
•
•
•
•
•
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
ARM Processor Support in ProASIC3E FPGAs
Pro (Professional) I/O
• 700 Mbps DDR, LVDS-Capable I/Os
Table 1-1 •
ProASIC3E Product Family
ProASIC3E Devices
Cortex-M1 Devices
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
CCCs with Integrated PLLs
VersaNet Globals
3
I/O Banks
Maximum User I/Os
Package Pins
PQFP
FBGA
2
1
A3PE600
600 k
13,824
108
24
1k
Yes
6
18
8
270
PQ208
FG256, FG484
A3PE1500
M1A3PE1500
1.5 M
38,400
270
60
1k
Yes
6
18
8
444
PQ208
FG484, FG676
A3PE3000
M1A3PE3000
3M
75,264
504
112
1k
Yes
6
18
8
620
PQ208
FG324
,
FG484, FG896
Notes:
1. Refer to the
product brief for more information.
2. The PQ208 package has six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the
handbook.
March 2008
© 2008 Actel Corporation
I
ACTEL [ Actel Corporation ]
