Actel Fusion Mixed-Signal FPGAs
Fusion Device Architecture Overview
Bank 0
Bank 1
CCC
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
OSC
I/Os
CCC/PLL
VersaTile
Bank 2
Bank 4
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Flash Memory Blocks
ADC
Flash Memory Blocks
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
CCC
Bank 3
Figure 1-1 •
Fusion Device Architecture Overview (AFS600)
Package I/Os: Single-/Double-Ended (Analog)
Fusion Devices
CoreMP7
ARM-Enabled Devices
QN108
QN180
PQ208
FG256
FG484
FG676
75/22 (20)
Cortex-M1
37/9 (16)
60/16 (20)
65/15 (24)
93/26 (24)
114/37 (24)
95/46 (40)
119/58 (40)
172/86 (40)
119/58 (40)
223/109 (40)
252/126 (40)
M1AFS250
AFS090
AFS250
AFS600
M7AFS600
M1AFS600
M1AFS1500
AFS1500
Note:
All devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).
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P r el im in ar y v 1 .7