Fast UART
Signal Descriptions
The following signal descriptions define the IO signals.
Signal
Direction Description
clk
reset_n
fuart_config.baudrate[15:0]
fuart_config.data_78
in
in
in
in
Memec Design
fuart_config.par_ebl
in
fuart_config.par_pol
in
fuart_config.stop_12
in
fuart_config.tx_run
in
fuart_config.rx_run
in
rx_pin
tx_pin
fuart_tx_data[7:0]
fuart_tx_we
in
out
in
in
fuart_tx_busy
out
fuart_rx_data[7:0]
out
fuart_rx_ready
fuart_par_error
out
out
fuart_form_error
out
System clock,
rising edge used only, must be at least 64 times higher than
maximum baudrate
Asynchronous system reset,
active low, goes to all flip flops
Baudrate
configuration value
Transmit and receive data size:
‘0’: use 7 bit data
‘1’: use 8 bit data
Parity enable:
‘0’: no parity check, no parity bit transmitted and received
‘1’: use parity check, parity bit inserted and checked
Parity polarity:
2
‘0’: use even parity
‘1’: use odd parity
This parameter is ignored when par_ebl is inactive!
Transmit and receive
stop bit number:
‘0’: use and check 1 stop bit
‘1’: use and check 2 stop bits
Transmit control:
‘0’: transmitter off, ignores all inputs, outputs inactive
‘1’: transmitter is working
Receive control:
‘0’: receiver off, ignores all inputs, outputs are inactive
‘1’: receiver is working
Pin for the
incoming bit stream.
The inactive state is logic ‘1’
Pin for the
outgoing bit stream.
The inactive state is logic ‘1’
8bit
data to be transmitted.
For 7bit configuration, bit[7] is ignored.
Data must be valid and stable when fuart_tx_we is active.
Event
for storing the
tx_data
in the transmit shift register and start of
transmission. It’s up to the system to not activate this input when the MC-ACT-
UARTF is busy.
When the transmitter is sending a byte, this
status output
remains active (logic
‘1’) until it is ready to send a new byte. While fuart_tx_busy is ‘1’, fuart_tx_we
mustn’t be activated.
8bit
data that has been received.
For 7bit configuration, bit[7] is ignored. The
data will be stable only during the active phase of fuart_rx_ready. Add a buffer
register if data should remain stable until reception of next character.
Event
(active ‘1’) for signalling, that a
new byte has arrived
and the
fuart_rx_data is valid now.
Event
(active ‘1’) for signalling, that a byte with
wrong parity
has been received
and aborted (it’s not visible at rx_ready)
This signal is always inactive when par_ebl is deactivated.
Event
(active ‘1’) for signalling, that a byte with
wrong format
has been
received and aborted (it’s not visible at rx_ready)
Table 2: Core I/O Signals
2
number of ones in a byte, including parity bit is even
February 25, 2003
Optimized for
5
ACTEL [ Actel Corporation ]
