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OTB25LPLH 参数 Datasheet PDF下载

OTB25LPLH图片预览
型号: OTB25LPLH
PDF下载: 下载PDF文件 查看货源
内容描述: 超快速的本地和长途线网络 [Ultra-Fast Local and Long-Line Network]
分类和应用:
文件页数/大小: 174 页 / 1510 K
品牌: ACTEL [ Actel Corporation ]
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v5.2
ProASIC
PLUS®
Flash Family FPGAs
Features and Benefits
High Capacity
Commercial and Industrial
75,000 to 1 Million System Gates
27 k to 198 kbits of Two-Port SRAM
66 to 712 User I/Os
300, 000 to 1 million System Gates
72 k to 198 kbits of Two Port SRAM
158 to 712 User I/Os
0.22 µm 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
Two Integrated PLLs
External System Performance up to 150 MHz
The Industry’s Most Effective Security Key (FlashLock
®
)
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
APA450
450,000
12,288
108 k
48
2
2
4
48
344
Yes
Yes
208
456
144, 256, 484
APA600
1
600,000
21,504
126 k
56
2
2
4
56
454
Yes
Yes
208
456
256, 484, 676
208, 352
624
APA750
750,000
32,768
144 k
64
2
2
4
64
562
Yes
Yes
208
456
676, 896
®
High Performance Routing Hierarchy
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
Schmitt-Trigger Option on Every Input
2.5 V/3.3 V Support with Individually-Selectable Voltage and
Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin Compatible Packages across the ProASIC
PLUS
Family
PLL with Flexible Phase, Multiply/Divide and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate Optimization
In-System Programming (ISP) via JTAG Port
ACTgen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
I/O
Military
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
Standard FPGA and ASIC Design Flow
ISP Support
SRAMs and FIFOs
Performance
Secure Programming
Low Power
Table 1 •
ProASIC
PLUS
Product Profile
Device
APA075
APA150
APA300
1
Maximum System Gates
75,000
150,000
300,000
Tiles (Registers)
3,072
6,144
8,192
Embedded RAM Bits (k=1,024 bits)
27 k
36k
72 k
Embedded RAM Blocks (256x9)
12
16
32
LVPECL
2
2
2
PLL
2
2
2
Global Networks
4
4
4
Maximum Clocks
24
32
32
Maximum User I/Os
158
242
290
JTAG ISP
Yes
Yes
Yes
PCI
Yes
Yes
Yes
Package
(by pin count)
TQFP
100, 144
100
PQFP
208
208
208
PBGA
456
456
FBGA
144
144, 256
144, 256
2
CQFP
208, 352
CCGA/LGA
2
Notes:
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
APA1000
1
1,000,000
56,320
198 k
88
2
2
4
88
712
Yes
Yes
208
456
896, 1152
208, 352
624
December 2005
© 2005 Actel Corporation
i