PLUS
ProASIC
Flash Family FPGAs
Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
RCLK
Cycle Start
RDB
RDATA
RPE
Old Data Out
New Valid Data Out
New RPE Out
Old RPE Out
EMPTY
FULL
EQTH, GETH
t
, t
t
ECBH FCBH
OCA
t
t
t
t
, t
RDCH
ECBA FCBA
t
t
RDCS
THCBH
t
RPCH
OCH
HCBA
t
RPCA
t
t
CML
CMH
t
CCYC
Note: The plot shows the normal operation status.
Figure 1-46 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 1-64 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
CCYC
Description
Min. Max. Units
Notes
Cycle time
7.5
3.0
ns
ns
ns
ns
ns
ns
CMH
Clock high phase
CML
Clock low phase
3.0
ECBA
New EMPTY access from RCLKS ↓
FULL ↓ access from RCLKS ↓
3.01
3.01
FCBA
ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold
THCBH
1.0
Empty/full/thresh are invalid from the end of
hold until the new access is complete
time from RCLKS ↓
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
2.0
ns
ns
ns
ns
ns
ns
ns
OCH
0.75
RDCH
RDCS
RPCA
RPCH
HCBA
Notes:
0.5
1.0
4.0
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
EQTH or GETH access from RCLKS ↓
1.0
4.5
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.
2. All –F speed grade devices are 20% slower than the standard numbers.
1-70
v5.2
ACTEL [ Actel Corporation ]
