Features
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Low-power Actel AGL600-FG256
IGLOO family FPGA
Micro-SD connector for Micro-SD
memory modules
SD/MMC Connector for SD, MMC4,
RS-MMC, Mini-SD, MMC Plus, RS
MMC Plus cards
On-board power regulators for 3.3 V
and 1.2/1.5 V core power
Interfaces with Marvell Littleton
PXA3xx VLIO interface using JAE
160-pin connectors
Flash*Freeze™ demonstration func-
tionality
FLASHPRO JTAG connector for pro-
gramming
Capability to measure current for
individual I/O banks and core
Meets SD Host Controller specifica-
tion Version 2.0 Part A2
Meets SDIO card v2.0 specification
Supports Embedded SDIO Specifica-
tion Version 0.92 Draft
Supports Test Register to generate
events by software
Supports high-capacity Ver2.00 Card
Supports non-DMA, SDMA, ADMA1,
and ADMA2 modes
Meets MMC specifications version
3.31 and 4.2
Supports MMCplus, MMCmobile
Meets CE-ATA Digital Protocol revi-
sion 1.1RC
Up to 200 Mbps with 4 parallel SD
data lines and 416 Mbps with 8 par-
allel MMC 4.2 data lines
Supports CE-ATA Digital Protocol
commands (CMD39/CMD60/CMD61)
Host clock rate from 0 to 52 MHz
CRC7 and CRC16 modules
Supports direct R/W (IO52) and
extended R/W (IO53) commands
Supports Read Wait Control, Sus-
pend/Resume operations
Storage Solution for Marvell’s
PXA300/310 Platform
Overview
The SD2.0/MMC4.2/CE-ATA storage solution has been developed in
cooperation with ARASAN Chip Systems for Actel AGL600-FG256 low-
power IGLOO FPGA. The Actel IGLOO family of reprogrammable, full-
featured flash FPGAs is designed to meet the demanding power and
area requirements of today's portable electronics. Based on the Actel
nonvolatile flash technology and single-chip ProASIC®3 FPGA archi-
tecture, the 1.2 V / 1.5 V operating voltage family offers the industry's
lowest power consumption - as low as 5 µW.
The storage daughter board interfaces with Marvell's PXA300/310
processor through the data flash interface (DFI). Arasan SD2.0/
MMC4.2/CE-ATA Host IP core in the Actel IGLOO device provides a
low-cost and low-power solution.
The Arasan SD2.0/MMC4.2/CE-ATA (CE-ATA 2) Host Controller core
consists of the SD 2.0, SDIO 2.0, MMC4.2, and CE-ATA 1.1 controllers.
The Arasan CE-ATA 2 Host is fully compliant with the SD Host specifi-
cation version 2.0 with Advanced-DMA support, MMC specification
version 4.2, and CE-ATA Digital Protocol revision 1.1RC. It supports SPI,
SD 1-bit, SD 4-bit, and MMC 8-bit modes. The CE-ATA 2 Host core is
designed to support high-speed and full-speed SD data transfers. In
application with an AHB interface, the Arasan CE-ATA 2 Host core
communicates with the ARM® processor at a clock speed up to 300
MHz. The CE-ATA 2 Host controller includes a DMA controller and a
FIFO that is expandable from a minimum size of 4 x 32-bit. An
optional CPRM functional block can be incorporated to perform a
Cipher algorithm for encryption and decryption.
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The Storage Solution Functional Block Diagram
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Copyright 2007 Arasan Chip Systems Inc.
Version 1.0
SD 2.0 Compliant
SDIO 2.0 Compliant
MMC 4.2 compliant
CE-ATA 1.1 compliant
ACTEL [ Actel Corporation ]
