Active-Semi
PIN DESCRIPTIONS
PIN
1
2
3
4, 17
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
EP
ACT8798
Rev 1, 16-Nov-09
NAME
OUT4
SCL
SDA
GA
nMSTR
nRSTO
OUT1
VP1
SW1
GP12
SW2
VP2
OUT2
ON3
PWRHLD
REFBP
OUT3
VP3
SW3
GP3
OUT5
OUT6
INL
EP
DESCRIPTION
Output Voltage for REG4. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650Ω load when disabled.
Clock Input for I
2
C Serial Interface. Data is read on the rising edge of the clock.
Data Input for I
2
C Serial Interface. Data is read on the rising edge of the clock.
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12, and GP3 together
at a single point as close to the IC as possible.
Master Enable Input. Drive nMSTR to GA or to a logic low to enable the IC. REG1, REG2, and
REG3 are enabled while nMSTR is asserted.
Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms whenever the
IC is enabled.
Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
Switching Node Output for REG1. Connect this pin to the switching end of the inductor.
Power Ground for REG1 and REG2. Connect GA, GP12, and GP3 together at a single point as
close to the IC as possible.
Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as
possible to the IC.
Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
Enable Input for REG3, ON3 is functional only when PWRHLD is driven high. Drive ON3 to a logic
high to turn on the REG3. Drive ON3 to a logic low to turn off the REG3.
Power Hold Input. Drive PWRHLD to logic high to enable the IC. Drive PWRHLD to a logic low to
disable all regulators.
Reference Noise Bypass. Connect a 0.01µF ceramic capacitor from REFBP to GA. This pin is dis-
charged to GA in shutdown.
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the inter-
nal feedback network to the output voltage.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as
possible to the IC.
Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the IC
as possible.
Output Voltage for REG5. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650Ω load when disabled.
Output Voltage for REG6. Capable of delivering up to 250mA of output current. The output is dis-
charged to G with 650Ω load when disabled.
Power Input for REG4, REG5 and REG6. Bypass to GA with a high quality ceramic capacitor
placed as close as possible to the IC.
Exposed Pad. Must be soldered to ground on PCB.
Innovative Power
TM
ActivePMU
TM
is a trademark of Active-Semi.
I
2
C
TM
is a trademark of Philips Electronics.
-4-
www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
