ACT8934A
Rev 1, 22-Oct-12
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NAME
REFBP
OUT1
GA
OUT4
OUT5
INL
OUT7
OUT6
nPBIN
PWRHLD
nRSTO
nIRQ
nPBSTAT
GP3
SW3
VP3
OUT3
PWREN
nLBO
LBI
ACIN
CHGLEV
DESCRIPTION
Reference Bypass. Connect a 0.047μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
Output Feedback Sense for REG1.
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12 and GP3
together at a single point as close to the IC as possible.
REG4 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic
capacitor from OUT4 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
REG5 output. Capable of delivering up to 150mA of output current. Connect a 1.5µF ceramic
capacitor from OUT5 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
Power Input for REG4, REG5, REG6, and REG7. Bypass to GA with a high quality ceramic
capacitor placed as close to the IC as possible.
REG7 output. Capable of delivering up to 250mA of output current. Connect a 2.2µF ceramic
capacitor from OUT7 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
REG6 output. Capable of delivering up to 250mA of output current. Connect a 2.2µF ceramic
capacitor from OUT6 to GA. The output is discharged to GA with 1.5kΩ resistor when disabled.
Master Enable Input. Drive nPBIN to GA through a 50kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a manual reset condition. Refer to the
nPBIN Multi-function Input
section
for more information. nPBIN is internally pulled up to VSYS through a 35kΩ resistor.
Power Hold Input. PWRHLD is internally pulled down to GA through a 500kΩ resistor. Refer to the
Control Sequences
section for more information.
Active Low Reset Output. See the
nRSTO Output
section for more information.
Open-Drain Interrupt Output. nIRQ is asserted any time an unmasked fault condition exists or a
charger interrupt occurs. See the
nIRQ Output
section for more information.
Active-Low Open-Drain Push-Button Status Output. nPBSTAT is asserted low whenever the
nPBIN is pushed, and is high-Z otherwise. See the
nPBSTAT Output
section for more information.
Power Ground for REG3. Connect GA, GP12, and GP3 together at a single point as close to the
IC as possible.
Switching Node Output for REG3.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close to the
IC as possible.
Output Feedback Sense for REG3.
Power Enable Input. Refer to the
Control Sequences
section for more information.
Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than
1.2V, and is high-Z otherwise. See the
Precision Voltage Detector
section for more information.
Low Battery Input. The input voltage is compared to 1.2V and the output of this comparison drives
nLBO. See the
Precision Voltage Detector
section for more information.
AC Input Supply Detection. See the
Charge Current Programming
section for more information.
Charge Current Selection Input. See the
Charge Current Programming
section for more information.
Innovative Power
TM
ActivePMU
TM
and
ActivePath
TM
are trademarks of Active-Semi.
I
2
C
TM
is a trademark of NXP.
-5-
www.active-semi.com
Copyright © 2012 Active-Semi, Inc.
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
