AD630 –Typical Performance Characteristics
20mV
100
90
50mV
50mV/DIV
(V
i
)
1mV/DIV
(A)
100
90
1mV
10V 20kHz
(V
i
)
1mV/DIV
(B)
10V/DIV
(V
o
)
100
90
10V
1mV
5 s
20mV/DIV
(V
o
)
20mV/DIV
(V
i
)
10
0%
10
0%
10
0%
20mV
TOP TRACE: Vo
BOTTOM TRACE: Vi
16
5k
15
2
20
19
18
10k
14
V
i
9
10
CH
B
CH
A
10k
500ns
100mV/DIV
(V
o
)
100mV
500ns
10V
TOP TRACE: Vi
MIDDLE TRACE: SETTLING
ERROR (B)
BOTTOM TRACE: Vo
10k
TOP TRACE: Vi
MIDDLE TRACE: SETTLING
ERROR (A)
BOTTOM TRACE: Vo
10k
13
12
V
O
V
i
TOP
TRACE
14 10k
15 20
2 CH A
12
13
10k
MIDDLE
TRACE
(A)
TEKTRONIX
7A13
V
O
BOTTOM
TRACE
V
i
TOP
TRACE
14
10k
15
20
2 CH A
12
10k
13
10k
V
O
BOTTOM
TRACE
(B)
MIDDLE
TRACE
1k
30pF
10k
HP5082-2811
Figure 7. Channel-to-Channel Switch-
Settling Characteristic
TWO WAYS TO LOOK AT THE AD630
Figure 8. Small Signal Noninverting
Step Response
Figure 9. Large Signal Inverting
Step Response
The functional block diagram of the AD630 (see page 1) also
shows the pin connections of the internal functions. An alternative
architectural diagram is shown in Figure 10. In this diagram, the
individual A and B channel preamps, the switch, and the inte-
grator output amplifier are combined in a single op amp. This
amplifier has two differential input channels, only one of which
is active at a time.
+V
S
15
11
14
V
i
16
R
A
5k
15
2
20
19
A
R
F
10k
13
B
V
O
R
B
10k
14
18
9
10
16
R
A
5k
1
2
20
19
18
17
R
B
10k
A
R
F
10k
13
2.5k
Figure 11. AD630 Symmetric Gain (
±
2)
B
2.5k
12
7
B/A
SEL B
9
SEL A
10
8
–V
S
Figure 10. Architectural Block Diagram
HOW THE AD630 WORKS
When channel B is selected, the resistors R
A
and R
F
are con-
nected for inverting feedback as shown in the inverting gain
configuration diagram in Figure 12. The amplifier has sufficient
loop gain to minimize the loading effect of R
B
at the virtual
ground produced by the feedback connection. When the sign of
the comparator input is reversed, input B will be deselected and
A will be selected. The new equivalent circuit will be the nonin-
verting gain configuration shown below. In this case R
A
will appear
across the op-amp input terminals, but since the amplifier drives
this difference voltage to zero the closed loop gain is unaffected.
The two closed loop gain magnitudes will be equal when R
F
/R
A
= 1 + R
F
/R
B
, which will result from making R
A
equal to R
F
R
B
/
(R
F
+ R
B
) the parallel equivalent resistance of R
F
and R
B
.
The 5k and the two 10k resistors on the AD630 chip can be
used to make a gain of two as shown here. By paralleling the
10k resistors to make R
F
equal 5k and omitting R
B
the circuit
can be programmed for a gain of
±
1 (as shown in Figure 18a).
These and other configurations using the on chip resistors
present the inverting inputs with a 2.5k source impedance. The
more complete AD630 diagrams show 2.5k resistors available at
the noninverting inputs which can be conveniently used to mini-
mize errors resulting from input bias currents.
–4–
REV. C
The basic mode of operation of the AD630 may be more easy to
recognize as two fixed gain stages which may be inserted into the
signal path under the control of a sensitive voltage comparator.
When the circuit is switched between inverting and noninverting
gain, it provides the basic modulation/demodulation function. The
AD630 is unique in that it includes Laser-Wafer-Trimmed thin-
film feedback resistors on the monolithic chip. The configuration
shown in Figure 11 yields a gain of
±2
and can be easily changed to
±1
by shifting R
B
from its ground connection to the output.
The comparator selects one of the two input stages to complete
an operational feedback connection around the AD630. The
deselected input is off and has negligible effect on the operation.
AD [ ANALOG DEVICES ]
