AD1981B
Reset Register (Index 00h)
Reg
No.
00h
Name
Reset
D15
X
D14
SE4
D13
SE3
D12
SE2
D11
SE1
D10
SE0
D9
ID9
D8
ID8
D7
ID7
D6
ID6
D5
ID5
D4
ID4
D3
ID3
D2
ID2
D1
ID1
D0
ID0
Default
0090h
NOTES
X in the above table is a wild card and has no effect on the value.
Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 74h, which forces the serial configuration).
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the following:
Bit
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Function
Dedicated Mic PCM In Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
AD1981B
0
0
0
0
1
0
0
1
0
0
SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are zeros).
Master Volume Register (Index 02h)
Reg
No.
02h
Name
Master
Volume
D15
D14
D13
X
D12
D11
D10
D9
D8
D7
D6
D5
X
D4
D3
D2
D1
D0
Default
MM X
LMV4 LMV3 LMV2 LMV1 LMV0 RM* X
RMV4 RMV3 RMV2 RMV1 RMV0 8000h
*
For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.
Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each
volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume
registers, to maintain compatibility whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically
set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.
RMV[4:0]
RM
LMV[4:0]
MM
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of 46.5 dB.
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the MM bit. Otherwise, this bit will always read 0 and will have no effect when set to 1.
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from
0 dB to a maximum attenuation of 46.5 dB.
Master Volume Mute. When this bit is set to 1, both the left and right channels are muted, unless the MSPLT
bit in Register 76h is set to 1, in which case this mute bit will affect only the left channel.
–10–
REV. B
AD [ ANALOG DEVICES ]
