AD603
APPLICATIONS
The circuit operates as follows. A1 and A2 are cascaded.
Capacitor C1 and the 100 Ω of resistance at the input of A1
form a time constant of 10 µs. C2 blocks the small dc offset
voltage at the output of A1 (which might otherwise saturate A2
at its maximum gain) and introduces a high-pass corner at
about 16 kHz, eliminating low frequency noise.
A LOW NOISE AGC AMPLIFIER
Figure 47 shows the ease with which the AD603 can be
connected as an AGC amplifier. The circuit illustrates many of
the points previously discussed: It uses few parts, has linear-in-
dB gain, operates from a single supply, uses two cascaded
amplifiers in sequential gain mode for maximum S/N ratio, and
an external resistor programs each amplifier’s gain. It also uses a
simple temperature-compensated detector.
A half-wave detector is used, based on Q1 and R8. The current
into capacitor CAV is just the difference between the collector
current of Q2 (biased to be 300 µA at 300 K, 27°C) and the
collector current of Q1, which increases with the amplitude of
the output signal.
The circuit operates from a single 10 V supply. Resistors R1, R2,
R3, and R4 bias the common pins of A1 and A2 at 5 V. This pin
is a low impedance point and must have a low impedance path
to ground, provided here by the 100 µF tantalum capacitors and
the 0.1 µF ceramic capacitors.
The automatic gain control voltage, VAGC, is the time integral of
this error current. In order for VAGC (and thus the gain) to
remain insensitive to short-term amplitude fluctuations in the
output signal, the rectified current in Q1 must, on average,
exactly balance the current in Q2. If the output of A2 is too
small to do this, VAGC will increase, causing the gain to increase,
until Q1 conducts sufficiently.
The cascaded amplifiers operate in sequential gain. Here, the
offset voltage between the Pin 2 (GNEG) of A1 and A2 is 1.05 V
(42.14 dB × 25 mV/dB), provided by a voltage divider
consisting of resistors R5, R6, and R7. Using standard values, the
offset is not exact, but it is not critical for this application.
Consider the case where R8 is zero and the output voltage VOUT
is a square wave at, say, 455 kHz, which is well above the corner
frequency of the control loop.
The gain of both A1 and A2 is programmed by resistors R13
and R14, respectively, to be about 42 dB; thus the maximum
gain of the circuit is twice that, or 84 dB. The gain control range
can be shifted up by as much as 20 dB by appropriate choices of
R13 and R14.
10V
C11
0.1µF
R9
1.54kΩ
R10
1.24kΩ
THIS CAPACITOR SETS
AGC TIME CONSTANT
C7
0.1µF
Q2
2N3906
V
AGC
10V
C8
R11
3.83kΩ
5V
0.1µF
R13
2.49kΩ
10V
8
C1
0.1µF
C
0.1µF
AV
8
Q1
2N3904
R14
2.49kΩ
C2
0.1µF
6
3
4
J1
C9
0.1µF
1
5
2
R12
4.99kΩ
RT
A1
R8
806Ω
10V
6
7
3
4
100Ω
AD603
5
2
A2
AD603
10V
7
J2
R1
2.49kΩ
1
C10
0.1µF
R3
2.49kΩ
2
+
1
C3
100µF
C4
0.1µF
R2
2.49kΩ
2
+
C5
100µF
C6
0.1µF
R4
2.49kΩ
AGC LINE
1V OFFSET FOR
SEQUENTIAL GAIN
R5
5.49kΩ
R7
3.48kΩ
10V
R6
1.05kΩ
5.5V
6.5V
1
2
RT PROVIDES A 50Ω INPUT IMPEDANCE.
C3 AND C5 ARE TANTALUM.
Figure 47. A Low Noise AGC Amplifier
Rev. G | Page 18 of 20
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