AD708
CROSSTALK PERFORMANCE OF THE AD708
The AD708 exhibits very low crosstalk as shown in Figures 24,
25 and 26. Figure 24 shows the offset voltage induced in side B
of the AD708 when side A’s output is moving slowly (0.2 Hz)
from –10 V to +10 V under no load. This is the least stressful
situation to the part since the overall power in the chip does not
change; only the location of the power in the output devices
changes. Figure 25 shows side B’s input offset voltage change
when side A is driving a 2 kΩ load. Here the power is being
changed in the chip with the maximum power change occurring
at
±
7.5 V. Figure 26 shows crosstalk under the most severe
conditions. Side A is connected as a follower with 0 V input,
and is now forced to sink and source
±
5 mA of output current
(Power = (30 V) (5 mA) = 150 mW). Even this large change in
power causes only an 8
µV
(linear) change in side B’s input
offset voltage.
OPERATION WITH A GAIN OF –100
To show the outstanding dc precision of the AD708 in real
application, Table I shows an error budget calculation for a gain
of –100 configuration shown in Figure 27.
Table I.
Maximum Error Contribution
A
V
= 100 (S Grade)
(Full Scale: V
OUT
= 10 V, V
IN
= 100 mV)
30
µV/100
mV
(100 kΩ)(1 nA)/10 V
10 V/(5*10
6
))/100 mV
0.35
µV/100
mV
(0.3
µV/°C)/100
mV
= 300 ppm
= 10 ppm
= 20 ppm
= 4 ppm
= 3 ppm/°C
= 334 ppm
+3 ppm/°C
Total Unadjusted
Error
With Offset
Calibrated Out
@ 25°C
–55°C to +125°C
@ 25°C
–55°C to +125°C
= 334 ppm > 11 Bits
= 634 ppm > 10 Bits
= 34 ppm > 14 Bits
= 334 ppm > 11 Bits
Figure 28. Precision PGA
Error Sources
V
OS
I
OS
Gain (2 kΩ load)
Noise
V
OS
Drift
are controlled by the select lines, A0 and A1 of the AD7502
multiplexer, and are 1, 10, 100 and 1000 in this design.
The input stage attains very high dc precision due to the 30
µV
maximum offset voltage match of the AD708S and the 1 nA
maximum input bias current match. The accuracy is maintained
over temperature because of the ultralow drift performance of
the AD708. The output stage uses an AD707J and well matched
resistors configured as a precision subtracter.
To achieve 0.1% gain accuracy, along with high common-mode
rejection, the circuit should be trimmed as follows:
To maximize common-mode rejection:
1. Set the select lines for Gain = 1 and ground V
INB
.
2. Apply a precision dc voltage to V
INA
and trim R
A
until
V
O
= –V
INA
to the required precision.
3. Next connect V
INB
to V
INA
and apply an input voltage equal
to the full-scale common-mode expected.
4. Trim R
B
until V
O
= 0 V.
To minimize gain errors:
1. Select Gain = 10 with the control lines and apply a differential
input voltage.
2. Adjust the 100
Ω
potentiometer such that V
O
= 10 V
IN
(adjust
V
IN
magnitude as necessary).
3. Repeat for Gain = 100 and Gain = 1000, adjusting 1 kΩ and
10 kΩ potentiometers, respectively.
Figure 27. Gain of –100 Configuration
This error budget assumes no error in the resistor ratio and no
error from power supply variation (the 120 dB minimum PSRR
of the AD708S makes this a good assumption). The external
resistors can cause gain error from mismatch and drift over
temperature.
High Precision Programmable Gain Amplifier
The design shown should allow for 0.1% gain accuracy and
0.1
µV/V
common-mode rejection when
±
1% resistors and
±
5%
potentiometers are used.
BRIDGE SIGNAL CONDITIONER
The three op amp programmable gain amplifier shown in Figure
28 takes advantage of the outstanding matching characteristics of
the AD708 to achieve high dc precision. The gains of the circuit
REV. B
–7–
The AD708 can be used in the circuit in Figure 29 to produce
an accurate and inexpensive dynamic bridge conditioner. The
low offset voltage match and low offset voltage drift match of
the AD708 combine to achieve circuit performance better than
all but the best instrumentation amplifiers. The AD708’s out-
standing specs: open loop gain, input offset currents and low
input bias currents, do not limit circuit accuracy.
AD [ ANALOG DEVICES ]
