AD7245A/AD7248A
The data held in the DAC latch determines the analog output of
the converter. Data is latched into the DAC latch on the rising
edge of
LDAC.
This
LDAC
signal is an asynchronous signal
and is independent of
WR.
This is useful in many applications.
However, in systems where the asynchronous
LDAC
can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. For ex-
ample, if
LDAC
goes LOW while
WR
is “LOW”, then the
LDAC
signal must stay LOW for t
7
or longer after
WR
goes
high to ensure correct data is latched through to the output.
Table I. AD7245A Truth Table
CLR
H
H
H
H
H
H
H
L
g
g
LDAC WR
L
H
H
H
H
L
g
X
H
L
H
X
L
g
H
H
X
H
CS
L
X
H
L
L
H
H
X
H
Function
Both Latches are Transparent
Both Latches are Latched
Both Latches are Latched
Input Latches Transparent
Input Latches Latched
DAC Latches Transparent
DAC Latches Latched
DAC Latches Loaded with all 0s
DAC Latches Latched with All
0s and Output Remains at
0 V or –5 V
Both Latches are Transparent
and Output Follows Input Data
Figure 5. AD7245A Write Cycle Timing Diagram
INTERFACE LOGIC INFORMATION—AD7248A
L
L
L
The input loading structure on the AD7248A is configured for
interfacing to microprocessors with an 8-bit wide data bus. The
part contains two 12-bit latches—an input latch and a DAC
latch. Only the data held in the DAC latch determines the ana-
log output from the converter. The truth table for AD7248A
operation is shown in Table II, while the input control logic dia-
gram is shown in Figure 6.
H = High State L = Low State X = Don’t Care
The contents of the DAC latch are reset to all 0s by a low level
on the
CLR
line. With both latches transparent, the
CLR
line
functions like a zero override with the output brought to 0 V in
the unipolar mode and –5 V in the bipolar mode for the dura-
tion of the
CLR
pulse. If both latches are latched, a “LOW”
pulse on the
CLR
input latches all 0s into the DAC latch and
the output remains at 0 V (or –5 V) after the
CLR
line has re-
turned “HIGH.” The
CLR
line can be used to ensure powerup
to 0 V on the AD7245A output in unipolar operation and is also
useful, when used as a zero override, in system calibration
cycles.
Figure 4 shows the input control logic for the AD7245A and the
write cycle timing for the part is shown in Figure 5.
Figure 6. AD7248A Input Control Logic
Figure 4. AD7245A Input Control Logic
CSMSB, CSLSB
and
WR
control the loading of data from the
external data bus to the input latch. The eight data inputs on
the AD7248A accept right justified data. This data is loaded to
the input latch in two separate write operations.
CSLSB
and
WR
control the loading of the lower 8-bits into the 12-bit wide
latch. The loading of the upper 4-bit nibble is controlled by
CSMSB
and
WR.
All control inputs are level triggered, and in-
put data for either the lower byte or upper 4-bit nibble is latched
into the input latches on the rising edge of
WR
(or either
CSMSB
or
CSLSB).
The order in which the data is loaded to
the input latch (i.e., lower byte or upper 4-bit nibble first) is not
important.
The
LDAC
input controls the transfer of 12-bit data from the
input latch to the DAC latch. This
LDAC
signal is also level
triggered, and data is latched into the DAC latch on the rising
edge of
LDAC.
The
LDAC
input is asynchronous and indepen-
dent of
WR.
This is useful in many applications especially in
REV. A
–9–
AD [ ANALOG DEVICES ]
