AD790–SPECIFICATIONS
DUAL SUPPLY
Parameter
RESPONSE CHARACTERISTIC
Propagation Delay, t
PD
OUTPUT CHARACTERISTICS
Output HIGH Voltage, V
OH
(Operation @ 25 C and +V
S
= 15 V, –V
S
= –15 V, V
LOGIC
= 5 V unless otherwise noted.)
Conditions
100 mV Step
5 mV Overdrive
T
MIN
to T
MAX
1.6 mA Source
6.4 mA Source
T
MIN
to T
MAX
1.6 mA Sink
6.4 mA Sink
T
MIN
to T
MAX
Min
AD790J/A
Typ Max
40
45
45/50
Min
AD790K/B
Typ Max
40
45
45/50
AD790S
Min Typ Max
40
45
60
Unit
ns
ns
4.3
4.3/4.3
4.65
4.45
0.35
0.44
4.3
4.3
0.5
0.5/0.5
1.0
1.5
0.6
5
6.5
0.25
0.3
4.65
4.45
0.35
0.44
4.3
4.3
0.5
0.5
0.25
0.5
0.5
3.5
4.5
0.15
0.2
4.65
4.45
0.35
0.44
Output LOW Voltage, V
OL
0.5
0.5
1.0
1.5
0.65
5
7
0.25
0.4
V
V
V
V
V
mV
mV
mV
µA
µA
µA
µA
dB
dB
INPUT CHARACTERISTICS
Offset Voltage
1
Hysteresis
2
Bias Current
Offset Current
T
MIN
to T
MAX
Power Supply
Rejection Ratio DC
Input Voltage Range
Differential Voltage
Common Mode
Common Mode
Rejection Ratio
V
S
±
20%
T
MIN
to T
MAX
V
S
≤±
15 V
–V
S
–10 V<V
CM
<+10 V
T
MIN
to T
MAX
80
76
80
76
T
MIN
to T
MAX
T
MIN
to T
MAX
Either Input
T
MIN
to T
MAX
0.3
0.2
0.4
2.5
0.04
0.05
0.3
0.4
1.8
0.02
0.2
0.3
0.4
2.5
0.04
90
88
V
S
+V
S
–2 V
95
90
20 2
25
5
35
10
0.8
88
85
100
93
80
76
V
S
+V
S
–2 V –V
S
90
85
–V
S
88
85
105
100
20 2
25
5
1.6
V
S
V
+V
S
–2 V V
95
88
20 2
25
5
35
10
0.8
5
8
dB
dB
MΩ pF
ns
ns
V
V
µA
µA
80
76
Input Impedance
LATCH CHARACTERISTICS
Latch Hold Time, t
H
Latch Setup Time, t
S
LOW Input Level, V
IL
HIGH Input Level, V
IH
Latch Input Current
SUPPLY CHARACTERISTICS
Diff Supply Voltage
3
Logic Supply
Quiescent Current
+V
S
–V
S
V
LOGIC
Power Dissipation
TEMPERATURE RANGE
Rated Performance
T
MIN
to T
MAX
T
MIN
to T
MA X
T
MIN
to T
MAX
V
LOGIC
= 5 V
T
MIN
to T
MAX
T
MIN
to T
MAX
+V
S
= 15 V
–V
S
= –15 V
V
LOGIC
= 5 V
35
10
0.8
1.6
3.5
5
1.6
2.3
5
7
2.3
2.3
4.5
4.0
8
4
2
33
7
10
5
3.3
242
4.5
4.0
8
4
2
33
7
10
5
3.3
242
4.7
4.2
8
4
2
33
7
10
5
3.3
242
V
V
mA
mA
mA
mW
°C
T
MIN
to T
MAX
0 to 70/–40 to +85
0 to 70/–40 to +85
–55 to +125
NOTES
1
Defined as the average of the input voltages at the low to high and high to low transition points. Refer to Figure 6.
2
Defined as half the magnitude between the input voltages at the low to high and high to low transition points. Refer to Figure 6.
3
+V
S
must be no lower than (V
LOGIC
–0.5 V) in any supply operating conditions, except during power up.
All min and max specifications are guaranteed. Specifications shown in
boldface
are tested on all production units at final test.
Specifications subject to change without notice.
–2–
REV. D
AD [ ANALOG DEVICES ]
