AD7943/AD7945/AD7948
AD7943 TIMING SPECIFICATIONS
1
(T
Parameter
t
STB2
t
DS
t
DH
t
SRI
t
LD
t
CLR
t
ASB
t
SV3
Limit @
V
DD
= +3 V to +3.6 V
60
15
35
55
55
55
0
60
40
10
25
35
35
35
0
35
A
= T
MIN
to T
MAX
, unless otherwise noted)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
STB Pulsewidth
Data Setup Time
Data Hold Time
SRI Data Pulsewidth
Load Pulsewidth
CLR Pulsewidth
Min Time Between Strobing Input Shift
Register and Loading DAC Register
STB Clocking Edge to SRO Data Valid Delay
Limit @
V
DD
= +4.5 V to +5.5 V
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1
µs
on any digital input.
2
STB mark/space ratio range is 60/40 to 40/60.
3
t
SV
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
t
STB
STB1,
STB2,
STB4
STB3
t
DH
t
DS
t
SRI
SRI
DB11(N)
(MSB)
DB10(N)
DB0(N)
t
ASB
LD1,
LD2,
CLR
SRO
t
LD,
t
CLR
t
SV
DB10(N–1)
DB0(N–1)
Figure 1. AD7943 Timing Diagram
1.6mA
I
OL
TO OUTPUT
PIN
+2.1V
C
L
50pF
200 A
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
REV. B
–5–
AD [ ANALOG DEVICES ]
