AD8310
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INLO
1
COMM
2
OFLT
3
VOUT
4
8
INHI
ENBL
01084-002
AD8310
TOP VIEW
(Not to Scale)
7
6
5
BFIN
VPOS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
INLO
COMM
OFLT
VOUT
VPOS
BFIN
ENBL
INHI
Function
One of Two Balanced Inputs. Biased roughly to VPOS/2.
Common Pin. Usually grounded.
Offset Filter Access. Nominally at about 1.75 V.
Low Impedance Output Voltage. Carries a 25 mA maximum load.
Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
Buffer Input. Used to lower post-detection bandwidth.
CMOS Compatible Chip Enable. Active when high.
Second of Two Balanced Inputs.
Rev. E | Page 5 of 24
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